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2003.5.26 8 h8/38024 , h8/38024 s, h8/38024f-ztat group hardware manual renesas 8-bit single-chip microcomputer h8 family/h8/300l super low power series rev.4.00

renesas 8-bit single-chip microcomputer h8 family/h8/300l super low power series h8/38024, h8/38024s, h8/38024f-ztat group hardware manual rej09b0042-0400o
rev. 4.00, 05/03, page iv of xl cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
rev. 4.00, 05/03, page v of xl preface the h8/38024 group is a single-chip microcomputer built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. the h8/38024 group incorporates peripheral functions including rom, ram, timer, serial communications interface (sci), 10-bit pwm, a/d converter, lcd controller/driver, and i/o ports. it is a microcomputer allowing the implementation of a sophisticated control system. versions are available with types of internal rom: flash memory (f-ztat? * 1 ) and prom (ztat? * 2 ). this makes it possible to design application products with a great deal of specification fluidity, and allows for rapid and flexible response to contingencies arising between the initial stages of production and full-scale production. notes: *1 f-ztat? is a trademark of renesas technology corp. *2 ztat? is a trademark of renesas technology corp. target readers: this manual is designed for use by people who design application systems using the h8/38024 group, h8/38024s group, and h8/38024f-ztat. to use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. purpose: this manual provides the information of the hardware functions and electrical characteristics of the h8/38024 group, h8/38024s group, and h8/38024f-ztat. the h8/300l series programming manual contains detailed information of executable instructions. please read the programming manual together with this manual. how to use the book: ? to understand general functions read the manual from the beginning. the manual explains the cpu, system control functions, peripheral functions and electrical characteristics in that order. ? to understanding cpu functions refer to the separate h8/300l series programming manual. explanatory note: bit sequence: upper bit at left, and lower bit at right list of related documents: the latest documents are available on our web site. please make sure that you have the latest version. (http://www.renesas.com/)
rev. 4.00, 05/03, page vi of xl ? user manual for h8/38024 group name of document document no. h8/38024 group, h8/38024s group, h8/38024f-ztat? hardware manual this manual h8/300l series programming manual ade-602-040 ? user manual for development tools name of document document no. h8s, h8/300 series, c/c++ compiler, assembler, optimizing linkage editor users manual ade-702-247 hitachi debugging interface users manual ade-702-161a high-performance embedded workshop ade-702-201a ? application note name of document document no. h8/300 series, h8/300l series software ade-502-052 notes: the following limitations apply to h8/38024 programming and debugging when the on- chip emulator (e10t) is used. 1. pin 95 is not available because it is used exclusively by the e10t. 2. pins 33, 34, and 35 are unavailable for use. in order to use these pins additional hardware must be mounted on the user board. 3. the address range h'7000 to h'7fff is used by the e10t and is unavailable to the user. 4. the address range h'f780 to h'fb7f must not be accessed under any circumstances. 5. when the e10t is being used, pin 95 is i/o, pins 33 and 34 are input, and pin 35 is output.
rev. 4.00, 05/03, page vii of xl list of items revised or added for this version item page revisions (see manual for details) all h8/38024s group added hd64338024s, hd64338023s, hd64338022s, hd64338021s, hd64338020s, hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, hcd64338020s hd64f38024r and hcd64f38024r added 1.1 overview table 1.1 features 1 to 3 description added 3rd line changed as follows within the h8/300l series, the h8/38024 group and h8/38024s group comprise 6th to 11th lines changed as follows together, these functions make the h8/38024 group and h8/38024s group ideally suited for embedded applications in systems requiring low power consumption and lcd display. models in the h8/38024 group and h8/38024s group are the h8/38024 and h8/38024s, with on-chip 32-kbyte rom and 1-kbyte ram, the h8/38023 and h8/38023s, with on-chip 24-kbyte rom and 1-kbyte ram, the h8/38022 and h8/38022s, with on-chip 16-kbyte rom and 1-kbyte ram, the h8/38021 and h8/38021s, with 12-kbyte rom and 512 byte ram, and the h8/38020 and h8/38020s, with 8-kbyte rom 15th line changed as follows table 1.1 summarizes the features of the h8/38024 group and h8/38024s group. cpu ? operating speed max. operating speed: 8 mhz (5 mhz for hd64f38024 and h8/38024s group) clock pulse generators two on-chip clock pulse generators ? system clock pulse generator: 1.0 to 16 mhz (1.0 to 10 mhz for hd64f38024 , hd64f38024r, and h8/38024s group) ? subclock pulse generator: 32.768 khz, 38.4 khz memory large on-chip memory ? h8/38024 and h8/38024s: 32-kbyte rom, 1-kbyte ram ? h8/38023 and h8/38023s: 24-kbyte rom, 1-kbyte ram ? h8/38022 and h8/38022s: 16-kbyte rom, 1-kbyte ram ? h8/38021 and h8/38021s: 12-kbyte rom, 512 byte ram ? h8/38020 and h8/38020s: 8-kbyte rom, 512 byte ram
rev. 4.00, 05/03, page viii of xl item page revisions (see manual for details) 5 product lineup amended 1.1 overview table 1.1 features item specification product code product lineup mask rom version ztat version f-ztat version package rom/ram size (byte) hd64338024 hd64738024 hd64f38024 r hd64f38024 fp-80a fp-80b tfp-80c (hd64f38024r and hd64f38024 only) tlp-85v (under development) (hd64f38024r only) die (mask rom/f- ztat version only) 32 k/1 k hd64338023 fp-80a fp-80b tfp-80c die 24 k/1 k hd64338022 fp-80a fp-80b tfp-80c die 16 k/1 k hd64338021 fp-80a fp-80b tfp-80c die 12 k/512 hd64338020 fp-80b tfp-80c die 8 k/512 hd64338024s fp-80a tfp-80c tlp-85v (under development) die 32 k/1 k hd64338023s fp-80a tfp-80c tlp-85v (under development) die 24 k/1 k hd64338022s fp-80a tfp-80c tlp-85v (under development) die 16 k/1 k hd64338021s fp-80a tfp-80c tlp-85v (under development) die 12 k/512 hd64338020s fp-80a tfp-80c tlp-85v (under development) die 8 k/512 refer to appendix e for information on product model numbers.
rev. 4.00, 05/03, page ix of xl item page revisions (see manual for details) 1.2 internal block diagram figure 1.1 block diagram 6 description added figure 1.1 shows a block diagram of h8/38024 group and h8/38024s group. figure amended large-current (25 ma/pin) high-voltage open-drain pin (7 v) large-current (10 ma/pin) (h8/38024s group only) large-current (10 ma/pin) high-voltage open-drain pin (7 v) large-current (10 ma/pin) (h8/38024s group only) high-voltage (7 v) input pin (except for h8/38024s group) note added if the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. 1.3.1 pin arrangement 7 description amended the h8/38024 group and h8/38024s group pin arrangements are shown in figures 1.2, 1.3, and 1.4. the bonding pad location diagram of the hcd64338024, hcd64338023, hcd64338022, hcd64338021 and hcd64338020 is shown in figure 1.5. the bonding pad coordinates of the hcd64338024, hcd64338023, hcd64338022, hcd64338021 and hcd64338020 are given in table 1.2. the bonding pad location diagram of the hcd64f38024, hcd64f38024r is shown in figure 1.6. the bonding pad coordinates of the hcd64f38024 are given in table 1.3. the bonding pad location diagram of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s is shown in figure 1.7. the bonding pad coordinates of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s are given in table 1.4. figure 1.2 pin arrangement (fp-80a, tfp-80c: top view) note added if the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. figure 1.3 pin arrangement (fp-80b: top view) 8 note added if the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. figure 1.4 pin arrangement (tlp-85v) [under development] 9 figure added figure 1.6 bonding pad location diagram of hcd64f38024, hcd64f38024r (top view) 12 figure title amended bonding pad location diagram of hcd64f38024, hcd64f38024r (top view) table 1.3 bonding pad coordinates of hcd64f38024, hcd64f38024r 13 table title amended bonding pad coordinates of hcd64f38024, hcd64f38024r
rev. 4.00, 05/03, page x of xl item page revisions (see manual for details) 1.3.1 pin arrangement figure 1.7 bonding pad location diagram of hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s (top view) table 1.4 bonding pad coordinates of hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s 14, 15 figure 1.7 and table 1.4 newly added 1.3.2 pin functions table 1.5 pin functions 16 table amended pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions power source pins v cc 52 54 e8 53 54 52 input power supply: all v cc pins should be connected to the system power supply. v ss 8 (= av ss ) 53 10 (= av ss ) 55 d8 e1 (= av ss ) 9 54 10 55 8 53 input ground: all v ss pins should be connected to the system power supply (0 v). av cc 1 3 b1 1 2 1 input analog power supply: this is the power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. av ss 8 (= v ss )10 (= v ss ) e1 (= v ss ) 8 9 8 input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0v). v 1 v 2 v 3 51 50 49 53 52 51 f9 e9 f8 52 51 50 53 52 51 51 50 49 input lcd power supply: these are the power supply pins for the l cd controller/driver. osc 1 10 12 f2 11 12 10 input clock pins osc 2 9 11 e3 10 11 9 output these pins connect to a crystal or ceramic oscillator, or can be used to input an e xternal clock. see section 4, clock pulse generators, for a typical connect ion diagram. x 1 6 8 d3 6 7 6 input x 2 7 9 d2 7 8 7 output these pins connect to a 32.768-khz or 38.4 -khz crystal oscillator. see section 4, clock pulse generators, for a typical connect ion diagram.
rev. 4.00, 05/03, page xi of xl item page revisions (see manual for details) 1.3.2 pin functions table 1.5 pin functions 17 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions system control res 12 14 f3 13 14 12 input reset: when this pin is driven low, the chip is reset test 11 13 e2 12 13 11 input test pin: this pin is reserved and cannot be used. it should be connected to v ss . interrupt pins irq 0 irq 1 irq 3 irq 4 72 76 5 3 74 78 7 5 c5 b3 d1 b2 73 77 5 3 74 78 6 4 72 76 5 3 input irq interrupt request 0, 1, 3, and 4: these are input pins for edge- sensitive external interrupts, with a selection of rising or falling edge irqaec 60 62 c10 61 62 60 input asynchronous event counter event signal: this is an interrupt input pin for enabling asynchronous event input. wkp 7 to wkp 0 20 to 13 22 to 15 h1, j1, h3, g1, h2, g2, f2, g3 21 to 14 22 to 15 20 to 13 input wakeup interrupt request 7 to 0: these are input pins for rising or falling-edge-sensitive external interrupts. timer pins aevl aevh 68 67 70 69 a6 b7 69 68 70 69 68 67 input asynchronous event counter event input: this is an event input pin for input to the asynchronous event counter. tmic 76 78 b3 77 78 76 input timer c event input: this is an event input pin for input to the timer c counter. ud 61 63 a9 62 63 61 input timer c up/down select: this pin selects up- or down-counting for the timer c counter. the counter operates as a down-counter when this pin is high, and as an up- counter when low. tmif 5 7 d1 5 6 5 input timer f event input: this is an event input pin for input to the timer f counter.
rev. 4.00, 05/03, page xii of xl item page revisions (see manual for details) 1.3.2 pin functions table 1.5 pin functions 18 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions timer pins tmofl 62 64 a8 63 64 62 output timer fl output: this is an output pin for waveforms generated by the timer fl output compare function. tmofh 63 65 b9 64 65 63 output timer fh output: this is an output pin for waveforms generated by the timer fh output compare function. tmig 2 4 c1 2 3 2 input timer g capture input: this is an input pin for timer g input capture. 10-bit pwm pin pwm1 pwm2 54 55 56 57 e10 d9 55 56 56 57 54 55 output 10-bit pwm output: these are output pins for waveforms generated by the channel 1 and 2 10-bit pwms. i/o ports p1 7 p1 6 p1 4 p1 3 5 4 3 2 7 6 5 4 d1 c2 b2 c1 5 4 3 2 6 5 4 3 5 4 3 2 i/o port 1: this is a 4-bit i/o port. input or output can be designated for each bit by means of port control register 1 (pcr1). p3 7 to p3 0 68 to 61 70 to 63 a6, b7 c7, a7 b8, b9 a8, a9 69 to 62 70 to 63 68 to 61 i/o port 3: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 3 (pcr3). if the on-chip emulator is used, pins 33, 34, and 35 are reserved for the emulator and not available to the user. p4 3 72 74 c5 73 74 72 input port 4 (bit 3): this is a 1- bit input port. p4 2 to p4 0 71 to 69 73 to 71 b6 b5 c6 72 to 70 73 to 71 71 to 69 i/o port 4 (bits 2 to 0 ): this is a 3-bit i/o port. input or output can be designated for each bit by means of port control regi ster 4 (pcr4). p5 7 to p5 0 20 to 13 22 to 15 h1, j1 h3, g1 h2, g2 f1, g3 21 to 14 22 to 15 20 to 13 i/o port 5: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 5 (pcr5).
rev. 4.00, 05/03, page xiii of xl item page revisions (see manual for details) 1.3.2 pin functions table 1.5 pin functions 19 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions i/o ports p6 7 to p6 0 28 to 21 30 to 23 k5, j4 h4, k4 j3, j2 k3, k2 29 to 22 30 to 23 28 to 21 i/o port 6: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 6 (pcr6). p7 7 to p7 0 36 to 29 38 to 41 j8, j7 k6, h7 h6, j7 h6, j5 j6, h5 37 to 30 38 to 31 36 to 29 i/o port 7: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 7 (pcr7). p8 7 to p8 0 44 to 37 46 to 39 h9, j9 h10, j10 k8, k9 h8, k7 45 to 38 46 to 39 44 to 37 i/o port 8: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 8 (pcr8). p9 5 to p9 0 59 to 54 61 to 56 b10, c8 d10, c9 d9, e10 60 to 55 61 to 56 59 to 54 output port 9: this is a 6-bit output port. if the on-chip emulator is used, pin 95 is reserved for the emulato r and not available to the user. in the case of the f-ztat version, pin 95 should not be left o pen in the user mode, and should instead be pulled up to high level. pa 3 to pa 0 45 to 48 47 to 50 g10 g8 g9 f10 46 to 49 47 to 50 45 to 48 i/o port a: this is a 4-bit i/o port. input or output can be designated for each bit by means of port cont rol register a (pcra). pb 7 to pb 0 80 to 73 2, 1, 80 to 75 a3, a2 c3, a4 b3, b4 a5, c4 81 to 74 1, 81 to 75 80 to 73 input port b: this is an 8-bit input port. rxd 32 70 72 b5 71 72 70 input sci3 receive data input: this is the sci3 data input pin. serial communi- cation (sci) txd 32 71 73 b6 72 73 71 output sci3 transmit data output: this is the sci3 data output pin. sck 32 69 71 c6 70 71 69 i/o sci3 clock i/o: this is the sci3 clock i/o pin.
rev. 4.00, 05/03, page xiv of xl item page revisions (see manual for details) 1.3.2 pin functions table 1.5 pin functions 20 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions a/d converter an 7 to an 0 80 to 73 2, 1, 80 to 75 a3, a2 c3, a4 b3, b4 a5, c4 81 to 74 1, 81 to 75 80 to 73 input analog input channels 7 to 0: these are analog data input channels to the a/d converter. adtrg 3 5 b2 3 4 3 input a/d converter trigger input: this is the external trigger input pin to the a/d converter. lcd controller/ driver com 4 to com 1 45 to 48 47 to 50 g10, g8 g9, f10 46 to 49 47 to 50 45 to 48 output lcd common output: these are the lcd common output pins. seg 32 to seg 1 44 to 13 46 to 15 h9, j9, h10, j10, k8, k9, h8, k7, j8, j7, k6, h7, h6, j5, j6, h5, k5, j4, h4, k4, j3, j2, k3, k2, h1, j1, h3, g1, h2, g2, f1, g3 45 to 14 46 to 15 44 to 13 output lcd segment output: these are the lcd segment output pins. nc nc a1, a10, d4, k2, k10 nc pin notes: * 1 pad number for hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020. * 2 pad number for hcd64f38024 and hcd64f38024r. * 3 pad number for hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s. 4 the tlp-85v is under development.
rev. 4.00, 05/03, page xv of xl item page revisions (see manual for details) 2.8.1 memory map 55 to 59 product names added to description the memory map of the h8/38024 and h8/38024s are shown in figure 2.16 (1), that of the h8/38023 and h8/38023s in figure 2.16 (2), that of the h8/38022 and h8/38022s in figure 2.16 (3), that of the h8/38021 and h8/38021s in figure 2.16 (4), and that of the h8/38020 and h8/38020s in figure 2.16 (5). product name added to title of figure 2.16 (1) and figure amended h8/38024 and h8/38024s memory map h'0000 h'0029 h'002a h'7fff h'7000 h'f020 h'f02b h'f740 h'f74f h'fb80 h'fb7f h'ff7f h'ff80 h'ffff interrupt vector area user area (1 kbyte) on-chip rom 32 kbytes (32768 bytes) 1024 bytes internal i/o register (128 bytes) (workarea for reprogramming flash memory: 1 kbyte) * 2 internal i/o register not used firmware for on-chip emulator * 1 h'f780 not used not used lcd ram (16 bytes) h'0000 h'0029 h'002a h'7fff h'f740 h'f74f h'fb80 h'ff7f h'ff80 h'ffff interrupt vector area hd64f38024, hd64f38024r (flash memory version) hd64338024 (mask rom version) hd64338024s (mask rom version) hd64738024 (prom version) on-chip rom 32 kbytes (32768 bytes) 1024 bytes on-chip ram internal i/o register (128 bytes) not used not used lcd ram (16 bytes) on-chip ram (2 kbytes) notes: * 1 not available to the user if the on-chip emulator is used. * 2 used by the programming control program when programming flash memory. also, not available to the user if the on-chip emulator is used. product name added to title of figure 2.16 (2) h8/38023 and h8/38023s memory map product name added to title of figure 2.16 (3) h8/38022 and h8/38022s memory map product name added to title of figure 2.16 (4) h8/38021 and h8/38021s memory map product name added to title of figure 2.16 (5) h8/38020 and h8/38020s memory map
rev. 4.00, 05/03, page xvi of xl item page revisions (see manual for details) 2.9.1 notes on data access figure 2.17 data size and number of states for access to and from on-chip peripheral modules 61 note amended notes: the example of the h8/38024 is shown here. * 1 this address is h'7fff in the h8/38024 and h8/38024s (32-kbyte on-chip rom), h'5fff in the h8/38023 and h8/38023s (24-kbyte on-chip rom), h'3fff in the h8/38022 and h8/38022s (16-kbyte on-chip rom), h'2fff in the h8/38021 and h8/38021s (12-kbyte on- chip rom), h'1fff in the h8/38020 and h8/38020s (8-kbyte on-chip rom). * 2 this address is h'fd80 in the h8/38021, h8/38021s, h8/38020, and h8/38020s (512 bytes of on-chip ram). * 3 internal i/o registers with addresses from h'f020 to h'f02b and on-chip ram with addresses from h'f780 to h'fb7f are installed on the hd64f38024 and hd64f38024r only. attempting to access these addresses on products other than the hd64f38024 and hd64f38024r will result in access to an empty area. 3.3.1 overview table 3.2 interrupt sources and their priorities 72 watchdog timer added to interrupt sources 4.5 note on oscillators figure 4.12 negative resistance measurement and circuit modification suggestions 104, 105 description and figure added 5.1 overview table 5.2 internal state in each operating mode 111 note amended * 1 register contents are retained, but output is high-impedance state. port 5 of the hd64f38024 retains the previous pin state. 5.3.1 transition to standby mode 118 description amended the i/o ports go to the high-impedance state. port 5 of the hd64f38024 retains the previous pin state. 5.3.4 standby mode transition and pin states 120 description amended at the same time, pins go to the high-impedance state (except pins for which the pull-up mos is designated as on). port 5 of the hd64f38024 retains the previous pin state. 6.1 overview 133 product names added to description 1st line changed as follows the h8/38024 and h8/38024s have 32 kbytes of on-chip mask rom, the h8/38023 and h8/38023s have 24 kbytes, the h8/38022 and h8/38022s have 16 kbytes, the h8/38021 and h8/38021s have 12 kbytes, and the h8/38020 and h8/38020s have 8 kbytes.
rev. 4.00, 05/03, page xvii of xl item page revisions (see manual for details) 6.2.2 socket adapter pin arrangement and memory map figure 6.2 socket adapter pin correspondence (with hn27c101) 135 figure amended pgm v cc v ss indicated in the figure should be left open. 58 54 3 13 77 56 57 61 55 10 8 75 76 p9 2 v cc av cc test pb 2 p9 0 p9 1 p9 5 v ss v ss = av ss x 1 pb 0 pb 1 6.5.1 features 144 description amended the features of the 32-kbyte flash memory built into hd64f38024 and hd64f38024r are summarized below. reprogramming description amended the hd64f38024r can be reprogrammed up to 1,000 times and the hd64f38024 up to 100 times. 6.7 on-board programming modes 153 description amended at reset-start in reset mode, the series of hd64f38024 and hd64f38024r 6.7.1 boot mode table 6.9 oscillating frequencies (f osc ) for which automatic adjustment of lsi bit rate is possible 155 table title amended oscillating frequencies ( f osc ) for which automatic adjustment of lsi bit rate is possible table amended oscillating frequencies ( f osc ) range of lsi 6.7.2 programming/ erasing in user program mode 156 description amended the term user mode refers to the status when a user program is being executed. on-board programming/erasing of an 6.10.1 socket adapter 163 description amended the socket adapter converts the pin allocation of the hd64f38024 and hd64f38024r to that of 6.10.2 programmer mode commands figure 6.12 socket adapter pin correspondence diagram 164 figure amended hd64f38024, hd64f38024r fp-80a tfp-80c fp-80b pin no. pin name
rev. 4.00, 05/03, page xviii of xl item page revisions (see manual for details) 7.1 overview 175 product names added to description the h8/38024, h8/38023, h8/38022, h8/38024s, h8/38023s, and h8/38022s have 1 kbyte of high-speed static ram on-chip, and the h8/38021, h8/38020, h8/38021s, and h8/38020s have 512 bytes. the ram is connected to the cpu by a 16-bit data bus, allowing high- speed 2-state access for both byte data and word data. 177, 178 note added 8.1 overview table 8.1 port functions port 3 p3 7 /aevl p3 6 /aevh asynchronous counter event inputs aevl, aevh pmr3 eccr p3 5 to p3 3 none p3 2 , tmofh p3 1 , tmofl timer f output compare output pmr3 ? 8-bit i/o port ? mos input pull-up option ? large-current port * 1 ? mos open drain output selectable (only p3 5 ) p3 0 /ud timer c count up/down selection input pmr3 port 9 p9 5 to p9 2 none ? 6-bit output port ? high-voltage, large-current port * 2 p9 1 , p9 0 / pwm2, pwm1 10-bit pwm output pmr9 ? high-voltage port * 2 irqaec none notes: * 1 applies to the hd64338024, hd64338023, hd64338022, hd64338021, hd64338020, and hd64738024 only. * 2 standard voltage on h8/38024s group. 8.5.4 pin states table 8.13 port 5 pin states 201 note amended note: * a high-level signal is output when the mos pull-up is in the on state. in the hd64f38024 the previous pin state is retained. 8.9.2 register configuration and description 2. port mode register 9 (pmr9) 213, 214 pmr9 amended and note added bit initial value read/write note: * readable/writable reserved bit in the h8/38024s group. 7 1 6 1 5 1 4 1 3 pioff/ * 0 r/w 0 pwm 1 0 r/w 2 w 1 pwm 2 0 r/w bit 3 description added this bit is reserved in the h8/38024s group. bit 3 note changed 296 bit 6 table amended 9.7.2 register configurations 7. event counter control/status register (eccsr) 1 ecl has overflowed setting condition: set when ecl overflows from h'ff to h'00 .
rev. 4.00, 05/03, page xix of xl item page revisions (see manual for details) 9.7.5 application notes 304 description amended 1. when reading the values in ech and ecl, the correct value will not be returned if the event counter increments during the read operation. therefore, if the counter is being used in the 8-bit mode, clear bits cueh and cuel in eccsr to 0 before reading ech or ecl. if the counter is being used in the 16-bit mode, clear cuel only to 0 before reading ech or ecl. 3. when using the clock in the 16-bit mode, set cueh to 1 first , then set crch to 1 in eccsr. or, set cueh and crch simultaneously before inputting the clock. after that, do not change the cueh value while using in the 16-bit mode. otherwise, an error counter increment may occur. also, to reset the counter, clear crch and crcl to 0 simultaneously or clear crcl and crch to 0 sequentially, in that order. 12.6.3 influences on absolute precision figure 12.6 analog input circuit example 383 a/d converter equivalent circuit amended 20 pf 13.3.4 boosting the lcd drive power supply figure 13.9 connection of external split- resistance 402 figure amended r r r r
rev. 4.00, 05/03, page xx of xl item page revisions (see manual for details) 14.1 h8/38024 ztat version and mask rom version absolute maximum ratings table 14.1 absolute maximum ratings 403 table amended item symbol value unit note power supply voltage v cc 0.3 to +7.0 v * 1 analog power supply voltage av cc 0.3 to +7.0 v programming voltage v pp 0.3 to +13.0 v input voltage ports other than port b and irqaec v in 0.3 to v cc +0.3 v port b av in 0.3 to av cc +0.3 v irqaec hv in 0.3 to +7.3 v port 9 pin voltage v p9 0.3 to +7.3 v operating temperature t opr 20 to +75 (regular specifications) c 40 to +85 (wide-range specifications) c storage temperature t stg 55 to +125 c notes: * 1 permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 14.2.2 dc characteristics table 14.2 dc characteristics 406 description amended. v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise indicated. table amended p9 0 to p9 2 0.5 v cc = 2.2 to 5.5 v i ol = 25 ma * 5 i ol = 15 ma 408 0.5 i ol = 10 ma * 6 411 note * 7 deleted 14.2.3 ac characteristics table 14.3 control signal timing 412, 414 description amended. v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise indicated. note * 4 deleted table 14.4 serial interface (sci3) timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise indicated. note deleted
rev. 4.00, 05/03, page xxi of xl item page revisions (see manual for details) 415 description amended. v cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) unless otherwise indicated. 14.2.4 a/d converter characteristics table 14.5 a/d converter characteristics 416 note * 5 deleted 14.2.5 lcd characteristics table 14.6 lcd characteristics 416 description amended. v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +75c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise specified. note * 3 deleted 417 title amended h8/38024 f-ztat version and h8/38024r f-ztat version absolute maximum ratings table amended port 9 pin voltage v p9 C0.3 to +7.3 v 14.3 h8/38024 f-ztat version and h8/38024r f-ztat version absolute maximum ratings table 14.7 absolute maximum ratings operating temperature t opr C20 to +75 * 2 (regular specifications) c C40 to +85 * 2 (wide-range specifications) +75 (products shipped as chips) * 3 c storage temperature t stg C55 to +125 c notes: * 1 permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. * 2 the operating temperature ranges for flash memory programming/erasing are t a = C20c to +75c. * 3 power may be applied when the temperature is between C20 and +75 c. 14.4 h8/38024 f-ztat version and h8/38024r f-ztat version electrical characteristics 418title amended h8/38024 f-ztat version and h8/38024r f-ztat version electrical characteristics
rev. 4.00, 05/03, page xxii of xl item page revisions (see manual for details) 14.4.2 dc characteristics table 14.8 dc characteristics 420, 422 to 425 table amended ? default conditions unless otherwise indicated amended v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v . ? active mode current dissipation, sleep mode current dissipation, subactive mode current dissipation, subsleep mode current dissipation, watch mode current dissipation, and standby mode current dissipation information changed ? sleep mode and subsleep mode internal state descriptions amended only on-chip timers operate note amended * 6 except for the package for the tlp-85v (under development). 14.4.3 ac characteristics table 14.9 control signal timing 426, 427 table amended ? default conditions unless otherwise indicated amended v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v . ? oscillation stabilization time information changed ? note * 3 amended and note * 4 added table 14.10 serial interface (sci3) timing 428 table amended ? default conditions unless otherwise indicated amended v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v . note deleted 429 table amended ? default conditions unless otherwise indicated amended v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v . absolute accuracy 2.0 4.0 lsb av cc = 2.7 v to 3.6 v 14.4.4 a/d converter characteristics table 14.11 a/d converter characteristics conversion time 12.4 124 s av cc = 2.7 v to 3.6 v note * 4 deleted
rev. 4.00, 05/03, page xxiii of xl item page revisions (see manual for details) 430 table amended ? default conditions unless otherwise indicated amended v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v . 0.5 3.0 9.0 m ? * 3 lcd power supply split- resistance r lcd between v 1 and v ss 1.5 3.0 7.0 * 4 14.4.5 lcd characteristics table 14.12 lcd characteristics liquid crystal display voltage v lcd v 1 2.2 3.6 v * 2 notes: * 1 the voltage drop from power supply pins v 1 , v 2 , v 3 , and vss to each segment pin or common pin. * 2 when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v cc v 1 v 2 v 3 v ss . * 3 applies to the hd64f38024. * 4 applies to the hd64f38024r. 14.4.6 flash memory characteristics [preliminary specifications] table 14.13 flash memory characteristics 431, 432 description amended av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, v cc = 2.7 v to 3.6 v (operating voltage range in reading), v cc = 3.0 v to 3.6 v (operating voltage range in programming/erasing), t a = C20 to +75c (operating temperature range in programming/erasing) table amended maximum number of reprogrammings n wec 1000 * 8 * 11 10000 * 9 times 100 * 8 * 12 10000 * 9 data retention time t drp 10 * 10 years * 8 the minimum number of times all characteristics are guaranteed following reprogramming. (the guarantee covers the range from 1 to the minimum value.) * 9 reference value at 25c. (guideline showing number of reprogrammings over which functioning will be retained under normal circumstances.) * 10 data retention characteristics within the range indicated in the specifications, including the minimum value for reprogrammings . * 11 applies to an operating voltage range when reading data of 3.0 to 3.6 v. * 12 applies to an operating voltage range when reading data of 2.7 to 3.6 v.
rev. 4.00, 05/03, page xxiv of xl item page revisions (see manual for details) 14.5 h8/38024s group mask rom version absolute maximum ratings 433 newly added 14.6 h8/38024s group mask rom version electrical characteristics 434 to 447 newly added 14.9 resonator equivalent circuit figure 14.8 resonator equivalent circuit (1) 451 figure title amended figure 14.8 resonator equivalent circuit (1) figure 14.9 resonator equivalent circuit (2) newly added a.1 instructions table a.1 instruction set 460 note (4) amended (4) the number of states required for execution is 4n + 9 (n = value of r4l). 4n + 8 for hd64f38024 and h8/38024s group. b.2 functions pmr9port mode register 9 517 description amended and note added p90/pwm1 pin function switch functions as p90 output pin functions as pwm1 output pin 0 1 p91/pwm2 pin function switch functions as p91 output pin functions as pwm2 output pin 0 1 p92 to p90 step-up circuit control large-current port step-up circuit is turned on large-current port step-up circuit is turned off 0 1 bit initial value read/write note: * readable/writable reserved bit in the h8/38024s group. 7 1 6 1 5 1 4 1 3 pioff/ * 0 r/w 0 pwm1 0 r/w 2 w 1 pwm2 0 r/w c.4 block diagram of port 5 figure c.4 port 5 block diagram 541 note added note: * the value of sby is fixed at 1 in the hd64f38024.
rev. 4.00, 05/03, page xxv of xl item page revisions (see manual for details) appendix d port states in the different processing states table d.1 port states overview 548 note added port reset sleep subsleep standby watch subactive active p1 7 , p1 6 , p1 4 , p1 3 high impedance retained retained high impedance * 1 retained functions functions p3 7 to p3 0 high impedance retained retained high impedance * 1 retained functions functions p4 3 to p4 0 high impedance retained retained high impedance retained functions functions p5 7 to p5 0 high impedance retained retained high impedance * 1 * 2 retained functions functions p6 7 to p6 0 high impedance retained retained high impedance * 1 retained functions functions p7 7 to p7 0 high impedance retained retained high impedance retained functions functions p8 7 to p8 0 high impedance retained retained high impedance retained functions functions p9 5 to p9 0 high impedance retained retained high impedance * 1 retained functions functions pa 3 to pa 0 high impedance retained retained high impedance retained functions functions pb 7 to pb 0 high impedance high impedance high impedance high impedance high impedance high impedance high impedance notes: *1 high level output when mos pull-up is in on state. * 2 in the hd64f38024 the previous pin state is retained.
rev. 4.00, 05/03, page xxvi of xl item page revisions (see manual for details) appendix e list of product codes table e.1 h8/38024 group product code lineup 549 table replaced product type product code mark code package (package code) h8/38024 hd64338024h hd64338024( *** )h 80-pin qfp (fp-80a) h8/38024 group mask rom versions regular specifications hd64338024f hd64338024( *** )f 80-pin qfp (fp-80b) hd64338024w hd64338024( *** )w 80-pin tqfp (tfp-80c) hcd64338024 die hd64338024d hd64338024( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338024e hd64338024( *** )f 80-pin qfp (fp-80b) hd64338024wi hd64338024( *** )w 80-pin tqfp (tfp-80c) hd64738024h hd64738024h 80-pin qfp (fp-80a) ztat versions regular specifications hd64738024f hd64738024f 80-pin qfp (fp-80b) hd64738024w hd64738024w 80-pin tqfp (tfp-80c) hd64738024d hd64738024h 80-pin qfp (fp-80a) wide-range specifications hd64738024e hd64738024f 80-pin qfp (fp-80b) hd64738024wi hd64738024w 80-pin tqfp (tfp-80c) hd64f38024h hd64f38024h 80-pin qfp (fp-80a) f-ztat versions regular specifications hd64f38024rh hd64f38024h hd64f38024f hd64f38024f 80-pin qfp (fp-80b) hd64f38024rf hd64f38024f hd64f38024w hd64f38024w 80-pin tqfp (tfp-80c) hd64f38024rw hd64f38024w hcd64f38024 die hcd64f38024r hd64f38024d hd64f38024h 80-pin qfp (fp-80a) wide-range specifications hd64f38024rd hd64f38024h hd64f38024e hd64f38024f 80-pin qfp (fp-80b) hd64f38024re hd64f38024f hd64f38024wi hd64f38024w 80-pin tqfp (tfp-80c) hd64f38024rwi hd64f38024w h8/38023 hd64338023h hd64338023( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338023f hd64338023( *** )f 80-pin qfp (fp-80b) hd64338023w hd64338023( *** )w 80-pin tqfp (tfp-80c) hcd64338023 die hd64f38024rlpv f38024rlpv 85-pin tflga (tlp-85v) hd64f38024rlpiv f38024rlpiv 85-pin tflga (tlp-85v) hd64338023d hd64338023( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338023e hd64338023( *** )f 80-pin qfp (fp-80b) hd64338023wi hd64338023( *** )w 80-pin tqfp (tfp-80c)
rev. 4.00, 05/03, page xxvii of xl item page revisions (see manual for details) appendix e list of product codes table e.1 h8/38024 group product code lineup 550 product type product code mark code package (package code) h8/38022 hd64338022h hd64338022( *** )h 80-pin qfp (fp-80a) h8/38024 group mask rom versions regular specifications hd64338022f hd64338022( *** )f 80-pin qfp (fp-80b) hd64338022w hd64338022( *** )w 80-pin tqfp (tfp-80c) hcd64338022 die hd64338022d hd64338022( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338022e hd64338022( *** )f 80-pin qfp (fp-80b) hd64338022wi hd64338022( *** )w 80-pin tqfp (tfp-80c) h8/38021 hd64338021h hd64338021( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338021f hd64338021( *** )f 80-pin qfp (fp-80b) hd64338021w hd64338021( *** )w 80-pin tqfp (tfp-80c) hcd64338021 die hd64338021d hd64338021( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338021e hd64338021( *** )f 80-pin qfp (fp-80b) hd64338021wi hd64338021( *** )w 80-pin tqfp (tfp-80c) h8/38020 hd64338020h hd64338020( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338020f hd64338020( *** )f 80-pin qfp (fp-80b) hd64338020w hd64338020( *** )w 80-pin tqfp (tfp-80c) hcd64338020 die hd64338020d hd64338020( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338020e hd64338020( *** )f 80-pin qfp (fp-80b) hd64338020wi hd64338020( *** )w 80-pin tqfp (tfp-80c) h8/38024s hd64338024sh hd64338024( *** )h 80-pin qfp (fp-80a) h8/38024s group mask rom versions regular specifications hd64338024sw hd64338024( *** )w 80-pin tqfp (tfp-80c) hd64338024slpv 338024s( *** )lpv 85-pin tflga (tlp-85v) hcd64338024s die hd64338024sd hd64338024( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338024swi hd64338024( *** )w 80-pin tqfp (tfp-80c) hd64338024slpiv 338024s( *** )lpiv 85-pin tflga (tlp-85v) h8/38023s hd64338023sh hd64338023( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338023sw hd64338023( *** )w 80-pin tqfp (tfp-80c) hd64338023slpv 338023s( *** )lpv 85-pin tflga (tlp-85v) hcd64338023s die hd64338023sd hd64338023( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338023swi hd64338023( *** )w 80-pin tqfp (tfp-80c) hd64338023slpiv 338023s( *** )lpiv 85-pin tflga (tlp-85v) h8/38022s hd64338022sh hd64338022( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338022sw hd64338022( *** )w 80-pin tqfp (tfp-80c) hd64338022slpv 338022s( *** )lpv 85-pin tflga (tlp-85v) hcd64338022s die hd64338022sd hd64338022( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338022swi hd64338022( *** )w 80-pin tqfp (tfp-80c) hd64338022slpiv 338022s( *** )lpiv 85-pin tflga (tlp-85v) 551 product type product code mark code package (package code) h8/38021s hd64338021sh hd64338021( *** )h 80-pin qfp (fp-80a) h8/38024s group mask rom versions regular specifications hd64338021sw hd64338021( *** )w 80-pin tqfp (tfp-80c) hd64338021slpv 338021s( *** )lpv 85-pin tflga (tlp-85v) hcd64338021s die hd64338021sd hd64338021( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338021s wi hd64338021( *** )w 80-pin tqfp (tfp-80c) hd64338021slpiv 338021s( *** )lpiv 85-pin tflga (tlp-85v) h8/38020s hd64338020sh hd64338020( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338020sw hd64338020( *** )w 80-pin tqfp (tfp-80c) hd64338020slpv 338020s( *** )lpv 85-pin tflga (tlp-85v) hcd64338020s die hd64338020sd hd64338020( *** )h 80-pin qfp (fp-80a) hd64338020slpiv 338020s( *** )lpiv 85-pin tflga (tlp-85v) wide-range specifications hd64338020swi hd64338020( *** )w 80-pin tqfp (tfp-80c) note: ( *** ) is the rom code. an 85-pin version of the tflga (tlp-85v) is under development.
rev. 4.00, 05/03, page xxviii of xl item page revisions (see manual for details) appendix f package dimensions figure f.4 tlp-85v package dimensions 552 description added dimensional drawings of the h8/38024 group and h8/38024s group packages fp-80a, fp-80b, and tfp-80c are shown in figures f.1, f.2, and f.3 below. 555 newly added appendix g specifications of chip form figure g.2 chip sectional figure of the hcd64f38024 and hcd64f38024r 556, 557 description amended the specifications of the chip form of the hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020 are shown in figure g.1. the specifications of the chip form of the hcd64f38024 and hcd64f38024r are shown in figure g.2. the specifications of the chip form of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s are shown in figure g.3. title amended chip sectional figure of the hcd64f38024 and hcd64f38024r figure g.3 chip sectional figure of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s newly added appendix h form of bonding pads 558 description amended the form of the bonding pads for the hcd64338024, hcd64338023, hcd64338022, hcd64338021, hcd64338020, hcd64f38024, hcd64f38024r, hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s is shown in figure h.1.
rev. 4.00, 05/03, page xxix of xl item page revisions (see manual for details) appendix i specifications of chip tray figure i.2 specifications of chip tray for the hcd64f38024 and hcd64f38024r 559 to 562 description amended the specifications of the chip tray for the hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020 are shown in figure i.1. the specifications of the chip tray for the hcd64f38024 and hcd64f38024r are shown in figure i.2. the specifications of the chip tray for the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s are shown in figure i.3. title amended specifications of chip tray for the hcd64f38024 and hcd64f38024r figure i.3 specifications of chip tray for the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s newly added
rev. 4.00, 05/03, page xxx of xl
rev. 4.00, 05/03, page xxxi of xl contents section 1 overview ............................................................................................................. 1 1.1 overview.................................................................................................................... ....... 1 1.2 internal block diagram..................................................................................................... 6 1.3 pin arrangement and functions........................................................................................ 7 1.3.1 pin arrangement .................................................................................................. 7 1.3.2 pin functions ....................................................................................................... 16 section 2 cpu ...................................................................................................................... 21 2.1 overview.................................................................................................................... ....... 21 2.1.1 features................................................................................................................ 21 2.1.2 address space...................................................................................................... 22 2.1.3 register configuration......................................................................................... 22 2.2 register descriptions ....................................................................................................... .23 2.2.1 general registers ................................................................................................. 23 2.2.2 control registers ................................................................................................. 23 2.2.3 initial register values.......................................................................................... 25 2.3 data formats................................................................................................................ ..... 25 2.3.1 data formats in general registers ...................................................................... 26 2.3.2 memory data formats ......................................................................................... 27 2.4 addressing modes ............................................................................................................ 28 2.4.1 addressing modes ............................................................................................... 28 2.4.2 effective address calculation ............................................................................. 30 2.5 instruction set ............................................................................................................. ...... 34 2.5.1 data transfer instructions.................................................................................... 36 2.5.2 arithmetic operations.......................................................................................... 38 2.5.3 logic operations.................................................................................................. 39 2.5.4 shift operations ................................................................................................... 39 2.5.5 bit manipulations................................................................................................. 41 2.5.6 branching instructions ......................................................................................... 45 2.5.7 system control instructions................................................................................. 47 2.5.8 block data transfer instruction........................................................................... 48 2.6 basic operational timing ................................................................................................. 50 2.6.1 access to on-chip memory (ram, rom)......................................................... 50 2.6.2 access to on-chip peripheral modules............................................................... 51 2.7 cpu states .................................................................................................................. ...... 53 2.7.1 overview.............................................................................................................. 53 2.7.2 program execution state...................................................................................... 54 2.7.3 program halt state............................................................................................... 54 2.7.4 exception-handling state .................................................................................... 54
rev. 4.00, 05/03, page xxxii of xl 2.8 memory map .................................................................................................................. .. 55 2.8.1 memory map ....................................................................................................... 55 2.9 application notes ........................................................................................................... .. 60 2.9.1 notes on data access .......................................................................................... 60 2.9.2 notes on bit manipulation................................................................................... 62 2.9.3 notes on use of the eepmov instruction .......................................................... 68 section 3 exception handling ......................................................................................... 69 3.1 overview.................................................................................................................... ....... 69 3.2 reset ....................................................................................................................... .......... 69 3.2.1 overview.............................................................................................................. 69 3.2.2 reset sequence .................................................................................................... 69 3.2.3 interrupt immediately after reset ........................................................................ 70 3.3 interrupts .................................................................................................................. ......... 71 3.3.1 overview.............................................................................................................. 71 3.3.2 interrupt control registers................................................................................... 73 3.3.3 external interrupts ............................................................................................... 83 3.3.4 internal interrupts................................................................................................. 84 3.3.5 interrupt operations ............................................................................................. 85 3.3.6 interrupt response time...................................................................................... 90 3.4 application notes ........................................................................................................... .. 91 3.4.1 notes on stack area use ..................................................................................... 91 3.4.2 notes on rewriting port mode registers............................................................. 92 3.4.3 method for clearing interrupt request flags ...................................................... 94 section 4 clock pulse generators ................................................................................... 97 4.1 overview.................................................................................................................... ....... 97 4.1.1 block diagram..................................................................................................... 97 4.1.2 system clock and subclock................................................................................. 97 4.2 system clock generator ................................................................................................... 98 4.3 subclock generator.......................................................................................................... . 101 4.4 prescalers .................................................................................................................. ........ 103 4.5 note on oscillators......................................................................................................... ... 104 4.5.1 definition of oscillation stabilization wait time ............................................... 105 4.5.2 notes on use of crystal oscillator element (excluding ceramic oscillator element)............................................................................................................... 107 section 5 power-down modes ........................................................................................ 109 5.1 overview.................................................................................................................... ....... 109 5.1.1 system control registers..................................................................................... 112 5.2 sleep mode .................................................................................................................. ..... 117 5.2.1 transition to sleep mode..................................................................................... 117 5.2.2 clearing sleep mode............................................................................................ 117
rev. 4.00, 05/03, page xxxiii of xl 5.2.3 clock frequency in sleep (medium-speed) mode.............................................. 118 5.3 standby mode ................................................................................................................ ... 118 5.3.1 transition to standby mode................................................................................. 118 5.3.2 clearing standby mode ....................................................................................... 118 5.3.3 oscillator stabilization time after standby mode is cleared.............................. 119 5.3.4 standby mode transition and pin states ............................................................. 120 5.3.5 notes on external input signal changes before/after standby mode.................. 121 5.4 watch mode.................................................................................................................. .... 123 5.4.1 transition to watch mode ................................................................................... 123 5.4.2 clearing watch mode .......................................................................................... 123 5.4.3 oscillator stabilizationtime after watch mode is cleared ................................. 123 5.4.4 notes on external input signal changes before/after watch mode .................... 123 5.5 subsleep mode............................................................................................................... ... 124 5.5.1 transition to subsleep mode ............................................................................... 124 5.5.2 clearing subsleep mode ...................................................................................... 124 5.6 subactive mode .............................................................................................................. .. 125 5.6.1 transition to subactive mode .............................................................................. 125 5.6.2 clearing subactive mode..................................................................................... 125 5.6.3 operating frequency in subactive mode............................................................. 125 5.7 active (medium-speed) mode ......................................................................................... 126 5.7.1 transition to active (medium-speed) mode....................................................... 126 5.7.2 clearing active (medium-speed) mode.............................................................. 126 5.7.3 operating frequency in active (medium-speed) mode...................................... 126 5.8 direct transfer ............................................................................................................. ..... 127 5.8.1 overview of direct transfer ................................................................................ 127 5.8.2 direct transition times ....................................................................................... 128 5.8.3 notes on external input signal changes before/after direct transition.............. 130 5.9 module standby mode...................................................................................................... 131 5.9.1 setting module standby mode ............................................................................ 131 5.9.2 clearing module standby mode .......................................................................... 131 section 6 rom ..................................................................................................................... 133 6.1 overview.................................................................................................................... ....... 133 6.1.1 block diagram..................................................................................................... 133 6.2 h8/38024 prom mode.................................................................................................... 134 6.2.1 setting to prom mode ....................................................................................... 134 6.2.2 socket adapter pin arrangement and memory map........................................... 134 6.3 h8/38024 programming.................................................................................................... 137 6.3.1 writing and verifying.......................................................................................... 137 6.3.2 programming precautions .................................................................................... 142 6.4 reliability of programmed data ....................................................................................... 143 6.5 flash memory overview................................................................................................... 144 6.5.1 features................................................................................................................ 14 4
rev. 4.00, 05/03, page xxxiv of xl 6.5.2 block diagram..................................................................................................... 145 6.5.3 block configuration............................................................................................. 146 6.5.4 register configuration......................................................................................... 147 6.6 descriptions of registers of the flash memory................................................................ 148 6.6.1 flash memory control register 1 (flmcr1)..................................................... 148 6.6.2 flash memory control register 2 (flmcr2)..................................................... 150 6.6.3 erase block register (ebr) ................................................................................ 151 6.6.4 flash memory power control register (flpwcr) ............................................ 151 6.6.5 flash memory enable register (fenr) .............................................................. 152 6.7 on-board programming modes........................................................................................ 153 6.7.1 boot mode ........................................................................................................... 154 6.7.2 programming/erasing in user program mode..................................................... 156 6.8 flash memory programming/erasing ............................................................................... 156 6.8.1 program/program-verify ..................................................................................... 157 6.8.2 erase/erase-verify............................................................................................... 160 6.8.3 interrupt handling when programming/erasing flash memory.......................... 160 6.9 program/erase protection ................................................................................................. 162 6.9.1 hardware protection ............................................................................................ 162 6.9.2 software protection.............................................................................................. 162 6.9.3 error protection.................................................................................................... 162 6.10 programmer mode ............................................................................................................ 163 6.10.1 socket adapter..................................................................................................... 163 6.10.2 programmer mode commands ............................................................................ 163 6.10.3 memory read mode ............................................................................................ 165 6.10.4 auto-program mode ............................................................................................ 168 6.10.5 auto-erase mode................................................................................................. 170 6.10.6 status read mode ................................................................................................ 171 6.10.7 status polling ....................................................................................................... 173 6.10.8 programmer mode transition time..................................................................... 173 6.10.9 notes on memory programming.......................................................................... 174 6.11 power-down states for flash memory............................................................................. 174 section 7 ram ..................................................................................................................... 175 7.1 overview.................................................................................................................... ....... 175 7.1.1 block diagram..................................................................................................... 175 section 8 i/o ports .............................................................................................................. 177 8.1 overview.................................................................................................................... ....... 177 8.2 port 1...................................................................................................................... ........... 179 8.2.1 overview.............................................................................................................. 179 8.2.2 register configuration and description............................................................... 179 8.2.3 pin functions ....................................................................................................... 184 8.2.4 pin states.............................................................................................................. 18 5
rev. 4.00, 05/03, page xxxv of xl 8.2.5 mos input pull-up.............................................................................................. 185 8.3 port 3...................................................................................................................... ........... 186 8.3.1 overview.............................................................................................................. 186 8.3.2 register configuration and description............................................................... 186 8.3.3 pin functions ....................................................................................................... 191 8.3.4 pin states.............................................................................................................. 19 2 8.3.5 mos input pull-up.............................................................................................. 192 8.4 port 4...................................................................................................................... ........... 193 8.4.1 overview.............................................................................................................. 193 8.4.2 register configuration and description............................................................... 193 8.4.3 pin functions ....................................................................................................... 195 8.4.4 pin states.............................................................................................................. 19 6 8.5 port 5...................................................................................................................... ........... 197 8.5.1 overview.............................................................................................................. 197 8.5.2 register configuration and description............................................................... 197 8.5.3 pin functions ....................................................................................................... 200 8.5.4 pin states.............................................................................................................. 20 1 8.5.5 mos input pull-up.............................................................................................. 201 8.6 port 6...................................................................................................................... ........... 202 8.6.1 overview.............................................................................................................. 202 8.6.2 register configuration and description............................................................... 202 8.6.3 pin functions ....................................................................................................... 204 8.6.4 pin states.............................................................................................................. 20 5 8.6.5 mos input pull-up.............................................................................................. 205 8.7 port 7...................................................................................................................... ........... 206 8.7.1 overview.............................................................................................................. 206 8.7.2 register configuration and description............................................................... 206 8.7.3 pin functions ....................................................................................................... 208 8.7.4 pin states.............................................................................................................. 20 8 8.8 port 8...................................................................................................................... ........... 209 8.8.1 overview.............................................................................................................. 209 8.8.2 register configuration and description............................................................... 209 8.8.3 pin functions ....................................................................................................... 211 8.8.4 pin states.............................................................................................................. 21 1 8.9 port 9...................................................................................................................... ........... 212 8.9.1 overview.............................................................................................................. 212 8.9.2 register configuration and description............................................................... 212 8.9.3 pin functions ....................................................................................................... 215 8.9.4 pin states.............................................................................................................. 21 5 8.10 port a..................................................................................................................... ........... 216 8.10.1 overview.............................................................................................................. 216 8.10.2 register configuration and description............................................................... 216 8.10.3 pin functions ....................................................................................................... 218
rev. 4.00, 05/03, page xxxvi of xl 8.10.4 pin states.............................................................................................................. 2 19 8.11 port b ..................................................................................................................... ........... 220 8.11.1 overview.............................................................................................................. 220 8.11.2 register configuration and description............................................................... 220 8.11.3 pin functions ....................................................................................................... 221 8.12 input/output data inversion function .............................................................................. 223 8.12.1 overview.............................................................................................................. 223 8.12.2 register configuration and descriptions ............................................................. 223 8.12.3 note on modification of serial port control register ......................................... 225 8.13 application note ........................................................................................................... .... 225 8.13.1 the management of the un-use terminal .......................................................... 225 section 9 timers .................................................................................................................. 227 9.1 overview.................................................................................................................... ....... 227 9.2 timer a..................................................................................................................... ........ 228 9.2.1 overview.............................................................................................................. 228 9.2.2 register descriptions ........................................................................................... 230 9.2.3 timer operation................................................................................................... 233 9.2.4 timer a operation states .................................................................................... 233 9.2.5 application note.................................................................................................. 234 9.3 timer c ..................................................................................................................... ........ 234 9.3.1 overview.............................................................................................................. 234 9.3.2 register descriptions ........................................................................................... 236 9.3.3 timer operation................................................................................................... 239 9.3.4 timer c operation states..................................................................................... 241 9.4 timer f ..................................................................................................................... ........ 242 9.4.1 overview.............................................................................................................. 242 9.4.2 register descriptions ........................................................................................... 245 9.4.3 cpu interface ...................................................................................................... 252 9.4.4 operation ............................................................................................................. 255 9.4.5 application notes ................................................................................................ 258 9.5 timer g..................................................................................................................... ........ 261 9.5.1 overview.............................................................................................................. 261 9.5.2 register descriptions ........................................................................................... 263 9.5.3 noise canceler..................................................................................................... 268 9.5.4 operation ............................................................................................................. 270 9.5.5 application notes ................................................................................................ 274 9.5.6 timer g application example............................................................................. 279 9.6 watchdog timer .............................................................................................................. . 280 9.6.1 overview.............................................................................................................. 280 9.6.2 register descriptions ........................................................................................... 281 9.6.3 timer operation................................................................................................... 285 9.6.4 watchdog timer operation states ....................................................................... 286
rev. 4.00, 05/03, page xxxvii of xl 9.7 asynchronous event counter (aec)................................................................................ 287 9.7.1 overview.............................................................................................................. 287 9.7.2 register configurations ....................................................................................... 290 9.7.3 operation ............................................................................................................. 299 9.7.4 asynchronous event counter operation modes.................................................. 303 9.7.5 application notes ................................................................................................ 304 section 10 serial communication interface ................................................................ 305 10.1 overview................................................................................................................... ........ 305 10.1.1 features................................................................................................................ 3 05 10.1.2 block diagram...................................................................................................... 307 10.1.3 pin configuration.................................................................................................. 308 10.1.4 register configuration.......................................................................................... 308 10.2 register descriptions ...................................................................................................... .. 309 10.2.1 receive shift register (rsr) ................................................................................ 309 10.2.2 receive data register (rdr) ................................................................................ 309 10.2.3 transmit shift register (tsr) ............................................................................... 310 10.2.4 transmit data register (tdr)............................................................................... 310 10.2.5 serial mode register (smr) ................................................................................. 311 10.2.6 serial control register 3 (scr3)........................................................................... 314 10.2.7 serial status register (ssr) .................................................................................. 318 10.2.8 bit rate register (brr) ......................................................................................... 322 10.2.9 clock stop register 1 (ckstpr1)........................................................................ 328 10.2.10 serial port control register (spcr).................................................................... 328 10.3 operation .................................................................................................................. ........ 330 10.3.1 overview.............................................................................................................. 330 10.3.2 operation in asynchronous mode ....................................................................... 334 10.3.3 operation in synchronous mode ......................................................................... 343 10.3.4 multiprocessor communication function............................................................ 350 10.4 interrupts ................................................................................................................. .......... 357 10.5 application notes .......................................................................................................... ... 358 section 11 10-bit pwm .................................................................................................... 363 11.1 overview................................................................................................................... ........ 363 11.1.1 features................................................................................................................ 3 63 11.1.2 block diagram..................................................................................................... 364 11.1.3 pin configuration................................................................................................. 364 11.1.4 register configuration......................................................................................... 365 11.2 register descriptions ...................................................................................................... .. 366 11.2.1 pwm control register (pwcrm) ...................................................................... 366 11.2.2 pwm data registers u and l (pwdrum, pwdrlm)...................................... 367 11.2.3 clock stop register 2 (ckstpr2)...................................................................... 367 11.3 operation .................................................................................................................. ........ 369
rev. 4.00, 05/03, page xxxv iii of xl 11.3.1 operation ............................................................................................................. 369 11.3.2 pwm operation modes ....................................................................................... 370 section 12 a/d converter ................................................................................................. 371 12.1 overview................................................................................................................... ........ 371 12.1.1 features................................................................................................................ 3 71 12.1.2 block diagram..................................................................................................... 372 12.1.3 pin configuration................................................................................................. 373 12.1.4 register configuration......................................................................................... 373 12.2 register descriptions ...................................................................................................... .. 374 12.2.1 a/d result registers (adrrh, adrrl)........................................................... 374 12.2.2 a/d mode register (amr) ................................................................................. 374 12.2.3 a/d start register (adsr).................................................................................. 376 12.2.4 clock stop register 1 (ckstpr1)...................................................................... 377 12.3 operation .................................................................................................................. ........ 378 12.3.1 a/d conversion operation .................................................................................. 378 12.3.2 start of a/d conversion by external trigger input............................................. 378 12.3.3 a/d converter operation modes......................................................................... 379 12.4 interrupts ................................................................................................................. .......... 379 12.5 typical use ................................................................................................................ ....... 379 12.6 application notes .......................................................................................................... ... 382 12.6.1 application notes ................................................................................................ 382 12.6.2 permissible signal source impedance ................................................................. 383 12.6.3 influences on absolute precision......................................................................... 383 section 13 lcd controller/driver ................................................................................. 385 13.1 overview................................................................................................................... ........ 385 13.1.1 features................................................................................................................ 3 85 13.1.2 block diagram..................................................................................................... 386 13.1.3 pin configuration................................................................................................. 387 13.1.4 register configuration......................................................................................... 387 13.2 register descriptions ...................................................................................................... .. 388 13.2.1 lcd port control register (lpcr)..................................................................... 388 13.2.2 lcd control register (lcr)............................................................................... 390 13.2.3 lcd control register 2 (lcr2).......................................................................... 392 13.2.4 clock stop register 2 (ckstpr2)...................................................................... 393 13.3 operation .................................................................................................................. ........ 394 13.3.1 settings up to lcd display ................................................................................. 394 13.3.2 relationship between lcd ram and display.................................................... 396 13.3.3 operation in power-down modes ....................................................................... 401 13.3.4 boosting the lcd drive power supply............................................................... 402
rev. 4.00, 05/03, page xxxix of xl section 14 electrical characteristics .............................................................................. 403 14.1 h8/38024 ztat version and mask rom version absolute maximum ratings............ 403 14.2 h8/38024 ztat version and mask rom version electrical characteristics ................. 404 14.2.1 power supply voltage and operating range....................................................... 404 14.2.2 dc characteristics ............................................................................................... 406 14.2.3 ac characteristics ............................................................................................... 412 14.2.4 a/d converter characteristics ............................................................................. 415 14.2.5 lcd characteristics............................................................................................. 416 14.3 h8/38024 f-ztat version and h8/38024r f-ztat version absolute maximum ratings ........................................................................................................................ ...... 417 14.4 h8/38024 f-ztat version and h8/38024r f-ztat version electrical characteristics 418 14.4.1 power supply voltage and operating range....................................................... 418 14.4.2 dc characteristics ............................................................................................... 420 14.4.3 ac characteristics ............................................................................................... 426 14.4.4 a/d converter characteristics ............................................................................. 429 14.4.5 lcd characteristics............................................................................................. 430 14.4.6 flash memory characteristics [preliminary specifications] ................................ 431 14.5 h8/38024s group mask rom version absolute maximum ratings.............................. 433 14.6 h8/38024s group mask rom version electrical characteristics ................................... 434 14.6.1 power supply voltage and operating range....................................................... 434 14.6.2 dc characteristics ............................................................................................... 436 14.6.3 ac characteristics ............................................................................................... 443 14.6.4 a/d converter characteristics ............................................................................. 446 14.6.5 lcd characteristics............................................................................................. 447 14.7 operation timing........................................................................................................... ... 448 14.8 output load circuit ........................................................................................................ .. 450 14.9 resonator equivalent circuit ............................................................................................ 451 14.10 usage note................................................................................................................ ........ 452 appendix a cpu instruction set .................................................................................... 453 a.1 instructions................................................................................................................ ........ 453 a.2 operation code map......................................................................................................... 4 61 a.3 number of execution states.............................................................................................. 463 appendix b internal i/o registers ................................................................................. 468 b.1 addresses ................................................................................................................... ....... 468 b.2 functions................................................................................................................... ........ 473 appendix c i/o port block diagrams ........................................................................... 529 c.1 block diagrams of port 1.................................................................................................. 52 9 c.2 block diagrams of port 3.................................................................................................. 53 2 c.3 block diagrams of port 4.................................................................................................. 53 7 c.4 block diagram of port 5 ................................................................................................... 54 1
rev. 4.00, 05/03, page xl of xl c.5 block diagram of port 6 ................................................................................................... 54 2 c.6 block diagram of port 7 ................................................................................................... 54 3 c.7 block diagram of port 8 ................................................................................................... 54 4 c.8 block diagrams of port 9.................................................................................................. 54 5 c.9 block diagram of port a .................................................................................................. 546 c.10 block diagram of port b .................................................................................................. 54 7 appendix d port states in the different processing states .................................... 548 appendix e list of product codes ................................................................................ 549 appendix f package dimensions .................................................................................. 552 appendix g specifications of chip form .................................................................... 556 appendix h form of bonding pads .............................................................................. 558 appendix i specifications of chip tray ..................................................................... 559
rev. 4.00, 05/03, page 1 of 562 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcomputers (mcu: microcomputer unit), built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/38024 group and h8/38024s group comprise single-chip microcomputers equipped with a lcd (liquid crystal display) controller/driver. other on-chip peripheral functions include six timers, a two-channel 10-bit pulse width modulator (pwm), a serial communication interface, and an a/d converter. together, these functions make the h8/38024 group and h8/38024s group ideally suited for embedded applications in systems requiring low power consumption and lcd display. models in the h8/38024 group and h8/38024s group are the h8/38024 and h8/38024s, with on-chip 32-kbyte rom and 1-kbyte ram, the h8/38023 and h8/38023s, with on-chip 24-kbyte rom and 1-kbyte ram, the h8/38022 and h8/38022s, with on-chip 16-kbyte rom and 1-kbyte ram, the h8/38021 and h8/38021s, with 12-kbyte rom and 512 byte ram, and the h8/38020 and h8/38020s, with 8- kbyte rom and 512 byte ram. the h8/38024 is also available in a ztat? * 1 version with on-chip prom which can be programmed as required by the user. the h8/38024 is also available in f-ztat? * 2 versions with on-chip flash memory which can be reprogrammed on board. table 1.1 summarizes the features of the h8/38024 group and h8/38024s group. notes: *1 ztat (zero turn around time) is a trademark of renesas technology corp. *2 f-ztat? is a trademark of renesas technology corp.
rev. 4.00, 05/03, page 2 of 562 table 1.1 features item specification cpu high-speed h8/300l cpu ? general-register architecture general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) ? operating speed ? max. operating speed: 8 mhz (5 mhz for hd64f38024 and h8/38024s group) ? add/subtract: 0.25 s (operating at 8 mhz), 0.4 s (operating at = 5 mhz) ? multiply/divide: 1.75 s (operating at 8 mhz), 2.8 s (operating at = 5 mhz) ? can run on 32.768 khz or 38.4 khz subclock ? instruction set compatible with h8/300 cpu ? instruction length of 2 bytes or 4 bytes ? basic arithmetic operations between registers ? mov instruction for data transfer between memory and registers ? typical instructions ? multiply (8 bits 8 bits) ? divide (16 bits 8 bits) ? bit accumulator ? register-indirect designation of bit position interrupts 22 interrupt sources ? 13 external interrupt sources (irq 4 , irq 3 , irq 1 , irq 0 , wkp 7 to wkp 0 , irqaec) ? 9 internal interrupt sources clock pulse generators two on-chip clock pulse generators ? system clock pulse generator: 1.0 to 16 mhz (1.0 to 10 mhz for hd64f38024, hd64f38024r, and h8/38024s group) ? subclock pulse generator: 32.768 khz, 38.4 khz
rev. 4.00, 05/03, page 3 of 562 item specification power-down modes seven power-down modes ? sleep (high-speed) mode ? sleep (medium-speed) mode ? standby mode ? watch mode ? subsleep mode ? subactive mode ? active (medium-speed) mode memory large on-chip memory ? h8/38024 and h8/38024s: 32-kbyte rom, 1-kbyte ram ? h8/38023 and h8/38023s: 24-kbyte rom, 1-kbyte ram ? h8/38022 and h8/38022s: 16-kbyte rom, 1-kbyte ram ? h8/38021 and h8/38021s: 12-kbyte rom, 512 byte ram ? h8/38020 and h8/38020s: 8-kbyte rom, 512 byte ram i/o ports 66 pins ? 51 i/o pins ? 9 input pins ? 6 output pins
rev. 4.00, 05/03, page 4 of 562 item specification timers six on-chip timers ? timer a: 8-bit timer count-up timer with selection of eight internal clock signals divided from the system clock ( ) * and four clock signals divided from the watch clock ( w ) * ? asynchronous event counter: 16-bit timer ? count-up timer able to count asynchronous external events independently of the mcu's internal clocks asynchronous external events can be counted (both rising and falling edge detection possible) ? timer c: 8-bit timer ? count-up/down timer with selection of seven internal clock signals or event input from external pin ? auto-reloading ? timer f: 16-bit timer ? can be used as two independent 8-bit timers ? count-up timer with selection of four internal clock signals or event input from external pin ? provision for toggle output by means of compare-match function ? timer g: 8-bit timer ? count-up timer with selection of four internal clock signals ? incorporates input capture function (built-in noise canceler) ? watchdog timer ? reset signal generated by overflow of 8-bit counter serial communication interface ? sci3: 8-bit synchronous/asynchronous serial interface incorporates multiprocessor communication function 10-bit pwm pulse-division pwm output for reduced ripple ? can be used as a 10-bit d/a converter by connecting to an external low- pass filter. a/d converter successive approximations using a resistance ladder ? 8-channel analog input pins ? conversion time: 31/ or 62/ per channel lcd controller/ driver lcd controller/driver equipped with a maximum of 32 segment pins and four common pins ? choice of four duty cycles (static, 1/2, 1/3, or 1/4) ? segment pins can be switched to general-purpose port function in 4-bit units
rev. 4.00, 05/03, page 5 of 562 item specification product lineup product code mask rom version ztat version f-ztat version package rom/ram size (byte) hd64338024 hd64738024 hd64f38024r hd64f38024 fp-80a fp-80b tfp-80c (hd64f38024r and hd64f38024 only) tlp-85v (under development) (hd64f38024r only) die (mask rom/f-ztat version only) 32 k/1 k hd64338023 fp-80a fp-80b tfp-80c die 24 k/1 k hd64338022 fp-80a fp-80b tfp-80c die 16 k/1 k hd64338021 fp-80a fp-80b tfp-80c die 12 k/512 hd64338020 fp-80b tfp-80c die 8 k/512 hd64338024s fp-80a tfp-80c tlp-85v (under development) die 32 k/1 k hd64338023s fp-80a tfp-80c tlp-85v (under development) die 24 k/1 k hd64338022s fp-80a tfp-80c tlp-85v (under development) die 16 k/1 k hd64338021s fp-80a tfp-80c tlp-85v (under development) die 12 k/512 hd64338020s fp-80a tfp-80c tlp-85v (under development) die 8 k/512 refer to appendix e for information on product model numbers. note: * see section 4, clock pulse generators, for the definition of and w .
rev. 4.00, 05/03, page 6 of 562 1.2 internal block diagram figure 1.1 shows a block diagram of the h8/38024 group and h8/38024s group. sub clock osc h8/300l cpu ram (512 1k) system clock osc rom (8 32k) timer-a timer-c timer-f timer-g asynchronous counter (16 bit) a/d (10 bit) serial communication interface (sci3) 10-bit pwm1 10-bit pwm2 lcd controller large-current (25 ma/pin) high-voltage open-drain pin (7 v) large-current (10 ma/pin) (h8/38024s group only) large-current (10 ma/pin) high-voltage open-drain pin (7 v) large-current (10 ma/pin) (h8/38024s group only) high-voltage (7 v) input pin (except for h8/38024s group) port a pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 p6 0 /seg 9 p6 1 /seg 10 p6 2 /seg 11 p6 3 /seg 12 p6 4 /seg 13 p6 5 /seg 14 p6 6 /seg 15 p6 7 /seg 16 p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / 0 osc 1 osc 2 x 1 x 2 p1 3 /tmig p1 4 / 4 / p1 6 p1 7 / 3 /tmif p3 0 /ud p3 1 /tmofl p3 2 /tmofh p3 3 p3 4 p3 5 p3 6 /aevh p3 7 /aevl p5 0 / 0 /seg 1 p5 1 / 1 /seg 2 p5 2 / 2 /seg 3 p5 3 / 3 /seg 4 p5 4 / 4 /seg 5 p5 5 / 5 /seg 6 p5 6 / 6 /seg 7 p5 7 / 7 /seg 8 pb 7 /an 7 pb 6 /an 6 pb 5 /an 5 pb 4 /an 4 pb 3 /an 3 / 1 /tmic pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 v 1 v 2 v 3 irqaec p9 5 p9 4 p9 3 p9 2 p9 1 /pwm 2 p9 0 /pwm 1 av cc wdt v ss v ss = av ss v cc test port 9 port 8 port 7 lcd power supply port b port 6 port 5 port 4 port 3 port 1 note: if the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. figure 1.1 block diagram
rev. 4.00, 05/03, page 7 of 562 1.3 pin arrangement and functions 1.3.1 pin arrangement the h8/38024 group and h8/38024s group pin arrangements are shown in figures 1.2, 1.3, and 1.4. the bonding pad location diagram of the hcd64338024, hcd64338023, hcd64338022, hcd64338021 and hcd64338020 is shown in figure 1.5. the bonding pad coordinates of the hcd64338024, hcd64338023, hcd64338022, hcd64338021 and hcd64338020 are given in table 1.2. the bonding pad location diagram of the hcd64f38024, hcd64f38024r is shown in figure 1.6. the bonding pad coordinates of the hcd64f38024 are given in table 1.3. the bonding pad location diagram of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s is shown in figure 1.7. the bonding pad coordinates of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s are given in table 1.4. fp-80a, tfp-80c (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p3 0 /ud p3 1 /tmofl p3 2 /tmofh p3 3 p3 4 p3 5 p3 6 /aevh p3 7 /aevl p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / 0 pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 / 1 /tmic pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 av cc p1 3 /tmig p1 4 / 4 / p1 6 p1 7 / 3 /tmif x 1 x 2 v ss =av ss osc 2 osc 1 test p5 0 / 0 /seg 1 p5 1 / 1 /seg 2 p5 2 / 2 /seg 3 p5 3 / 3 /seg 4 p5 4 / 4 /seg 5 p5 5 / 5 /seg 6 p5 6 / 6 /seg 7 p5 7 / 7 /seg 8 p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 irqaec p9 5 p9 4 p9 3 p9 2 p9 1 /pwm 2 p9 0 /pwm 1 v ss v cc v 1 v 2 v 3 pa 0 /com 1 pa 1 /com 2 pa 2 /com 3 pa 3 /com 4 p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 note: if the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. figure 1.2 pin arrangement (fp-80a, tfp-80c: top view)
rev. 4.00, 05/03, page 8 of 562 fp-80b (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 p3 2 /tmofh p3 3 p3 4 p3 5 p3 6 /aevh p3 7 /aevl p4 0 /sck 32 p4 1 /rxd 32 p4 2 /txd 32 p4 3 / 0 pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 / 1 /tmic pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 av cc p1 3 /tmig p1 4 / 4 / p1 6 p1 7 / 3 /tmif x 1 x 2 v ss =av ss osc 2 osc 1 test p5 0 / 0 /seg 1 p5 1 / 1 /seg 2 p5 2 / 2 /seg 3 p5 3 / 3 /seg 4 p5 4 / 4 /seg 5 p5 5 / 5 /seg 6 p5 6 / 6 /seg 7 p5 7 / 7 /seg 8 p6 0 /seg 9 p6 1 /seg 10 p8 1 /seg 26 p8 0 /seg 25 p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p3 1 /tmofl p3 0 /ud irqaec p9 5 p9 4 p9 3 p9 2 p9 1 /pwm 2 p9 0 /pwm 1 v ss v cc v 1 v 2 v 3 pa 0 /com 1 pa 1 /com 2 pa 2 /com 3 pa 3 /com 4 p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 p8 3 /seg 28 p8 2 /seg 27 note: if the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. figure 1.3 pin arrangement (fp-80b: top view)
rev. 4.00, 05/03, page 9 of 562 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d8 d9 d10 e1 e2 e3 e8 e9 e10 f1 f2 f3 f8 f9 f10 g1 g2 g3 g8 g9 g10 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 tlp-85v (top view) (under development) note: pins are shown in transparent view. figure 1.4 pin arrangement (tlp-85v) [under development]
rev. 4.00, 05/03, page 10 of 562 y x (0, 0) 61 59 57 55 53 51 49 47 45 43 60 58 56 54 52 50 48 46 44 42 81 79 77 75 73 71 69 67 65 63 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 22 23 80 78 76 74 72 70 68 66 64 62 25 27 29 31 33 35 37 39 41 24 26 28 30 32 34 36 38 40 chip size: 3.99 mm 3.99 mm voltage level on the back of the chip: gnd type code figure 1.5 bonding pad location diagram of hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020 (top view)
rev. 4.00, 05/03, page 11 of 562 table 1.2 bonding pad coordinates of hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020 coordinates coordinates pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1av cc C1870 1546 42 p84/seg29 1870 C1571 2 p13/tmig C1870 1274 43 p85/seg30 1870 C1395 3 p14/ irq4 / adtrg C1870 1058 44 p86/seg31 1870 C1251 4 p16 C1870 909 45 p87/seg32 1870 C1111 5 p17/ irq3 /tmif C1870 759 46 pa3/com4 1870 C970 6 x1 C1870 608 47 pa2/com3 1870 C831 7 x2 C1870 475 48 pa1/com2 1870 C691 8av ss C1870 304 49 pa0/com1 1870 C550 9v ss C1870 173 50 v3 1870 C410 10 osc2 C1870 C10 51 v2 1870 C270 11 osc1 C1870 C150 52 v1 1870 C131 12 test C1870 C290 53 v cc 1870 10 13 res C1870 C425 54 v ss 1870 150 14 p50/ wkp0 /seg1 C1870 C560 55 p90/pwm1 1870 293 15 p51/ wkp1 /seg2 C1870 C695 56 p91/pwm2 1870 489 16 p52/ wkp2 /seg3 C1870 C831 57 p92 1870 685 17 p53/ wkp3 /seg4 C1870 C966 58 p93 1870 880 18 p54/ wkp4 /seg5 C1870 C1101 59 p94 1870 1076 19 p55/ wkp5 /seg6 C1870 C1236 60 p95 1870 1274 20 p56/ wkp6 /seg7 C1870 C1379 61 irqaec 1870 1546 21 p57/ wkp7 /seg8 C1870 C1561 62 p30/ud 1782 1872 22 p60/seg9 C1780 C1872 63 p31/tmofl 1621 1872 23 p61/seg10 C1621 C1872 64 p32/tmofh 1084 1872 24 p62/seg11 C1037 C1872 65 p33 948 1872 25 p63/seg12 C896 C1872 66 p34 810 1872 26 p64/seg13 C765 C1872 67 p35 673 1872 27 p65/seg14 C635 C1872 68 p36/aevh 536 1872 28 p66/seg15 C502 C1872 69 p37/aevl 311 1872 29 p67/seg16 C371 C1872 70 p40/sck32 176 1872 30 p70/seg17 C239 C1872 71 p41/rxd32 38 1872 31 p71/seg18 C108 C1872 72 p42/txd32 C99 1872 32 p72/seg19 23 C1872 73 p43/ irq0 C234 1872 33 p73/seg20 156 C1872 74 pb0/an0 C482 1872 34 p74/seg21 287 C1872 75 pb1/an1 C614 1872 35 p75/seg22 419 C1872 76 pb2/an2 C745 1872 36 p76/seg23 550 C1872 77 pb3/an3/ irq1 /tmic C878 1872 37 p77/seg24 682 C1872 78 pb4/an4 C1008 1872 38 p80/seg25 833 C1872 79 pb5/an5 C1148 1872 39 p81/seg26 1040 C1872 80 pb6/an6 C1621 1872 40 p82/seg27 1621 C1872 81 pb7/an7 C1782 1872 41 p83/seg28 1782 C1872 notes: v ss pads (no. 8 and 9) should be connected to power supply lines. test pad (no. 12) should be connected to v ss . if the pad of these arent connected to the power supply line, the lsi will not operate correctly. these values show the coordinates of the centers of pads. the accuracy is 5 m. the home-point position is the chips center and the center is located at half the distance between the upper and lower pads and left and right pads.
rev. 4.00, 05/03, page 12 of 562 63 61 59 57 55 53 51 49 47 45 43 62 60 58 56 54 52 50 48 46 44 42 81 79 77 75 73 71 69 67 65 80 78 76 74 72 70 68 66 64 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 26 25 28 30 32 34 36 38 40 27 29 31 33 35 37 39 41 y x (0, 0) type code chip size: 3.84 mm 4.24 mm voltage level on the back of the chip: gnd : nc pad figure 1.6 bonding pad location diagram of hcd64f38024, hcd64f38024r (top view)
rev. 4.00, 05/03, page 13 of 562 table 1.3 bonding pad coordinates of hcd64f38024, hcd64f38024r coordinates coordinates pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 pb7/an7 C1802 1904 42 p83/seg28 1802 C1898 2av cc C1802 1717 43 p84/seg29 1802 C1750 3 p13/tmig C1802 1443 44 p85/seg30 1802 C1594 4 p14/ irq4 / adtrg C1802 1292 45 p86/seg31 1802 C1454 5 p16 C1802 1157 46 p87/seg32 1802 C1296 6 p17/ irq3 /tmif C1802 1022 47 pa3/com4 1802 C1182 7 x1 C1802 887 48 pa2/com3 1802 C1068 8 x2 C1802 753 49 pa1/com2 1802 C954 9av ss C1802 638 50 pa0/com1 1802 C840 10 v ss C1802 473 51 v3 1802 C726 11 osc2 C1802 318 52 v2 1802 C534 12 osc1 C1802 202 53 v1 1802 C402 13 test C1802 69 54 v cc 1802 C267 14 res C1802 C63 55 v ss 1802 C126 15 p50/ wkp0 /seg1 C1802 C195 56 p90/pwm1 1802 206 16 p51/ wkp1 /seg2 C1802 C355 57 p91/pwm2 1802 457 17 p52/ wkp2 /seg3 C1802 C514 58 p92 1802 707 18 p53/ wkp3 /seg4 C1802 C674 59 p93 1802 958 19 p54/ wkp4 /seg5 C1802 C844 60 p94 1802 1209 20 p55/ wkp5 /seg6 C1802 C1008 61 p95 1802 1460 21 p56/ wkp6 /seg7 C1802 C1348 62 irqaec 1802 1710 22 p57/ wkp7 /seg8 C1802 C1709 63 p30/ud 1802 1904 23 p60/seg9 C1802 C1904 64 p31/tmofl 1686 1999 24 p61/seg10 C1686 C1999 65 p32/tmofh 1222 1999 25 p62/seg11 C1198 C1999 66 p33 1077 1999 26 p63/seg12 C1057 C1999 67 p34 932 1999 27 p64/seg13 C916 C1999 68 p35 788 1999 28 p65/seg14 C755 C1999 69 p36/aevh 643 1999 29 p66/seg15 C625 C1999 70 p37/aevl 498 1999 30 p67/seg16 C493 C1999 71 p40/sck32 353 1999 31 p70/seg17 C352 C1999 72 p41/rxd32 226 1999 32 p71/seg18 C202 C1999 73 p42/txd32 63 1999 33 p72/seg19 C69 C1999 74 p43/ irq0 C82 1999 34 p73/seg20 72 C1999 75 pb0/an0 C229 1999 35 p74/seg21 213 C1999 76 pb1/an1 C404 1999 36 p75/seg22 330 C1999 77 pb2/an2 C577 1999 37 p76/seg23 459 C1999 78 pb3/an3/ irq1 /tmic C751 1999 38 p77/seg24 583 C1999 79 pb4/an4 C925 1999 39 p80/seg25 730 C1999 80 pb5/an5 C1099 1999 40 p81/seg26 937 C1999 81 pb6/an6 C1686 1999 41 p82/seg27 1686 C1999 notes: v ss pads (no. 9 and 10) should be connected to power supply lines. test pad (no. 13) should be connected to v ss . if the pad of these arent connected to the power supply line, the lsi will not operate correctly. these values show the coordinates of the centers of pads. the accuracy is 5 m. the home-point position is the chips center and the center is located at half the distance between the upper and lower pads and left and right pads.
rev. 4.00, 05/03, page 14 of 562 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (0.0) y x chip size: 2.91 mm 2.91 mm voltage level on the back of the chip: gnd figure 1.7 bonding pad location diagram of hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s (top view)
rev. 4.00, 05/03, page 15 of 562 table 1.4 bonding pad coordinates of hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s coordinates coordinates pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1av cc C1338 1053 41 p84/seg29 1338 C1121 2 p13/tmig C1338 823 42 p85/seg30 1338 C929 3 p14/ irq4 / adtrg C1338 737 43 p86/seg31 1338 C820 4 p16 C1338 649 44 p87/seg32 1338 C721 5 p17/ irq3 /tmif C1338 556 45 pa3/com4 1338 C610 6 x1 C1338 460 46 pa2/com3 1338 C499 7 x2 C1338 363 47 pa1/com2 1338 C388 8v ss = av ss C1338 229 48 pa0/com1 1338 C277 9 osc2 C1338 100 49 v3 1338 C189 10 osc1 C1338 13 50 v2 1338 C91 11 test C1338 C74 51 v1 1338 6 12 res C1338 C168 52 v cc 1338 156 13 p50/ wkp0 /seg1 C1338 C265 53 v ss 1338 362 14 p51/ wkp1 /seg2 C1338 C373 54 p90/pwm1 1338 528 15 p52/ wkp2 /seg3 C1338 C481 55 p91/pwm2 1338 614 16 p53/ wkp3 /seg4 C1338 C590 56 p92 1338 699 17 p54/ wkp4 /seg5 C1338 C698 57 p93 1338 785 18 p55/ wkp5 /seg6 C1338 C806 58 p94 1338 871 19 p56/ wkp6 /seg7 C1338 C892 59 p95 1338 957 20 p57/ wkp7 /seg8 C1338 C1091 60 irqaec 1338 1147 21 p60/seg9 C1121 C1338 61 p30/ud 1131 1338 22 p61/seg10 C927 C1338 62 p31/tmofl 936 1338 23 p62/seg11 C805 C1338 63 p32/tmofh 831 1338 24 p63/seg12 C703 C1338 64 p33 735 1338 25 p64/seg13 C593 C1338 65 p34 631 1338 26 p65/seg14 C483 C1338 66 p35 526 1338 27 p66/seg15 C372 C1338 67 p36/aevh 421 1338 28 p67/seg16 C263 C1338 68 p37/aevl 317 1338 29 p70/seg17 C166 C1338 69 p40/sck32 212 1338 30 p71/seg18 C47 C1338 70 p41/rxd32 108 1338 31 p72/seg19 55 C1338 71 p42/txd32 3 1338 32 p73/seg20 166 C1338 72 p43/ irq0 C101 1338 33 p74/seg21 277 C1338 73 pb0/an0 C249 1338 34 p75/seg22 388 C1338 74 pb1/an1 C362 1338 35 p76/seg23 499 C1338 75 pb2/an2 C476 1338 36 p77/seg24 610 C1338 76 pb3/an3/ irq1 /tmic C589 1338 37 p80/seg25 701 C1338 77 pb4/an4 C702 1338 38 p81/seg26 790 C1338 78 pb5/an5 C791 1338 39 p82/seg27 885 C1338 79 pb6/an6 C880 1338 40 p83/seg28 1076 C1338 80 pb7/an7 C1081 1338 note: pad no. 11 (test) should be connected to v ss . if it is not connected, the lsi will not operate correctly. these values show the coordinates of the centers of pads. the accuracy is 5 m. the home-point position is the chips center and the center is located at halfway between the upper and lower pads and the left and right pads.
rev. 4.00, 05/03, page 16 of 562 1.3.2 pin functions table 1.5 outlines the pin functions of the h8/38024 group. table 1.5 pin functions pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions power source pins v cc 52 54 e8 53 54 52 input power supply: all v cc pins should be connected to the system power supply. v ss 8 (= av ss ) 53 10 (= av ss ) 55 d8 e1 (= av ss ) 9 54 10 55 8 53 input ground: all v ss pins should be connected to the system power supply (0 v). av cc 1 3 b1 1 2 1 input analog power supply: this is the power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. av ss 8 (= v ss )10 (= v ss ) e1 (= v ss ) 8 9 8 input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0v). v 1 v 2 v 3 51 50 49 53 52 51 f9 e9 f8 52 51 50 53 52 51 51 50 49 input lcd power supply: these are the power supply pins for the lcd controller/driver. osc 1 10 12 f2 11 12 10 input clock pins osc 2 9 11 e3 10 11 9 output these pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. see section 4, clock pulse generators, for a typical connection diagram. x 1 6 8 d3 6 7 6 input x 2 7 9 d2 7 8 7 output these pins connect to a 32.768-khz or 38.4-khz crystal oscillator. see section 4, clock pulse generators, for a typical connection diagram.
rev. 4.00, 05/03, page 17 of 562 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions system control res 12 14 f3 13 14 12 input reset: when this pin is driven low, the chip is reset test 11 13 e2 12 13 11 input test pin: this pin is reserved and cannot be used. it should be connected to v ss . interrupt pins irq 0 irq 1 irq 3 irq 4 72 76 5 3 74 78 7 5 c5 b3 d1 b2 73 77 5 3 74 78 6 4 72 76 5 3 input irq interrupt request 0, 1, 3, and 4: these are input pins for edge- sensitive external interrupts, with a selection of rising or falling edge irqaec 60 62 c10 61 62 60 input asynchronous event counter event signal: this is an interrupt input pin for enabling asynchronous event input. wkp 7 to wkp 0 20 to 13 22 to 15 h1, j1, h3, g1, h2, g2, f2, g3 21 to 14 22 to 15 20 to 13 input wakeup interrupt request 7 to 0: these are input pins for rising or falling-edge-sensitive external interrupts. timer pins aevl aevh 68 67 70 69 a6 b7 69 68 70 69 68 67 input asynchronous event counter event input: this is an event input pin for input to the asynchronous event counter. tmic 76 78 b3 77 78 76 input timer c event input: this is an event input pin for input to the timer c counter. ud 61 63 a9 62 63 61 input timer c up/down select: this pin selects up- or down-counting for the timer c counter. the counter operates as a down-counter when this pin is high, and as an up- counter when low. tmif 5 7 d1 5 6 5 input timer f event input: this is an event input pin for input to the timer f counter.
rev. 4.00, 05/03, page 18 of 562 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions timer pins tmofl 62 64 a8 63 64 62 output timer fl output: this is an output pin for waveforms generated by the timer fl output compare function. tmofh 63 65 b9 64 65 63 output timer fh output: this is an output pin for waveforms generated by the timer fh output compare function. tmig 2 4 c1 2 3 2 input timer g capture input: this is an input pin for timer g input capture. 10-bit pwm pin pwm1 pwm2 54 55 56 57 e10 d9 55 56 56 57 54 55 output 10-bit pwm output: these are output pins for waveforms generated by the channel 1 and 2 10-bit pwms. i/o ports p1 7 p1 6 p1 4 p1 3 5 4 3 2 7 6 5 4 d1 c2 b2 c1 5 4 3 2 6 5 4 3 5 4 3 2 i/o port 1: this is a 4-bit i/o port. input or output can be designated for each bit by means of port control register 1 (pcr1). p3 7 to p3 0 68 to 61 70 to 63 a6, b7 c7, a7 b8, b9 a8, a9 69 to 62 70 to 63 68 to 61 i/o port 3: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 3 (pcr3). if the on-chip emulator is used, pins 33, 34, and 35 are reserved for the emulator and not available to the user. p4 3 72 74 c5 73 74 72 input port 4 (bit 3): this is a 1- bit input port. p4 2 to p4 0 71 to 69 73 to 71 b6 b5 c6 72 to 70 73 to 71 71 to 69 i/o port 4 (bits 2 to 0): this is a 3-bit i/o port. input or output can be designated for each bit by means of port control register 4 (pcr4). p5 7 to p5 0 20 to 13 22 to 15 h1, j1 h3, g1 h2, g2 f1, g3 21 to 14 22 to 15 20 to 13 i/o port 5: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 5 (pcr5).
rev. 4.00, 05/03, page 19 of 562 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions i/o ports p6 7 to p6 0 28 to 21 30 to 23 k5, j4 h4, k4 j3, j2 k3, k2 29 to 22 30 to 23 28 to 21 i/o port 6: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 6 (pcr6). p7 7 to p7 0 36 to 29 38 to 41 j8, j7 k6, h7 h6, j7 h6, j5 j6, h5 37 to 30 38 to 31 36 to 29 i/o port 7: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 7 (pcr7). p8 7 to p8 0 44 to 37 46 to 39 h9, j9 h10, j10 k8, k9 h8, k7 45 to 38 46 to 39 44 to 37 i/o port 8: this is an 8-bit i/o port. input or output can be designated for each bit by means of port control register 8 (pcr8). p9 5 to p9 0 59 to 54 61 to 56 b10, c8 d10, c9 d9, e10 60 to 55 61 to 56 59 to 54 output port 9: this is a 6-bit output port. if the on-chip emulator is used, pin 95 is reserved for the emulator and not available to the user. in the case of the f-ztat version, pin 95 should not be left open in the user mode, and should instead be pulled up to high level. pa 3 to pa 0 45 to 48 47 to 50 g10 g8 g9 f10 46 to 49 47 to 50 45 to 48 i/o port a: this is a 4-bit i/o port. input or output can be designated for each bit by means of port control register a (pcra). pb 7 to pb 0 80 to 73 2, 1, 80 to 75 a3, a2 c3, a4 b3, b4 a5, c4 81 to 74 1, 81 to 75 80 to 73 input port b: this is an 8-bit input port. rxd 32 70 72 b5 71 72 70 input sci3 receive data input: this is the sci3 data input pin. serial communi- cation (sci) txd 32 71 73 b6 72 73 71 output sci3 transmit data output: this is the sci3 data output pin. sck 32 69 71 c6 70 71 69 i/o sci3 clock i/o: this is the sci3 clock i/o pin.
rev. 4.00, 05/03, page 20 of 562 pin no. type symbol fp-80a tfp-80c fp-80b tlp-85v * 4 pad no. * 1 pad no. * 2 pad no. * 3 i/o name and functions a/d converter an 7 to an 0 80 to 73 2, 1, 80 to 75 a3, a2 c3, a4 b3, b4 a5, c4 81 to 74 1, 81 to 75 80 to 73 input analog input channels 7 to 0: these are analog data input channels to the a/d converte. adtrg 3 5 b2 3 4 3 input a/d converter trigger input: this is the external trigger input pin to the a/d converter. lcd controller/ driver com 4 to com 1 45 to 48 47 to 50 g10, g8 g9, f10 46 to 49 47 to 50 45 to 48 output lcd common output: these are the lcd common output pins. seg 32 to seg 1 44 to 13 46 to 15 h9, j9, h10, j10, k8, k9, h8, k7, j8, j7, k6, h7, h6, j5, j6, h5, k5, j4, h4, k4, j3, j2, k3, k2, h1, j1, h3, g1, h2, g2, f1, g3 45 to 14 46 to 15 44 to 13 output lcd segment output: these are the lcd segment output pins. nc nc a1, a10, d4, k2, k10 nc pin notes: * 1 pad number for hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020. * 2 pad number for hcd64f38024 and hcd64f38024r. * 3 pad number for hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s. * 4 the tlp-85v is under development.
rev. 4.00, 05/03, page 21 of 562 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300l cpu are listed below. ? general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers ? instruction set with 55 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct ? register indirect ? register indirect with displacement ? register indirect with post-increment or pre-decrement ? absolute address ? immediate ? program-counter relative ? memory indirect ? 64-kbyte address space ? high-speed operation ? all frequently used instructions are executed in two to four states ? high-speed arithmetic and logic operations ? 8- or 16-bit register-register add or subtract: 0.25 s * ? 8 8-bit multiply: 1.75 s * ? 16 8-bit divide: 1.75 s * note: * these values are at = 8 mhz. ? low-power operation modes sleep instruction for transfer to low-power operation
rev. 4.00, 05/03, page 22 of 562 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. see section 2.8, memory map, for details of the memory map. 2.1.3 register configuration figure 2.1 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers (cr) 753210 64 figure 2.1 cpu registers
rev. 4.00, 05/03, page 23 of 562 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.2, sp (r7) points to the top of the stack. lower address side [h0000] upper address side [hffff] unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). program counter (pc) this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0).
rev. 4.00, 05/03, page 24 of 562 condition code register (ccr) this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. bit 7interrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see section 3.3, interrupts. bit 6user bit (u): can be used freely by the user. bit 5half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4user bit (u): can be used freely by the user. bit 3negative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2zero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. refer to the h8/300l series programming manual for the action of each instruction on the flag bits.
rev. 4.00, 05/03, page 25 of 562 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. ? bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). ? all arithmetic and logic instructions except adds and subs can operate on byte data. ? the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. ? the daa and das instructions perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit.
rev. 4.00, 05/03, page 26 of 562 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2.3. 7 6 5 4 3 2 1 0 dont care data type register no. data format 70 1-bit data rnh 76543210 dont care 70 1-bit data rnl msb lsb dont care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl notation: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb dont care 70 msb lsb 15 0 upper digit lower digit dont care 70 3 4 dont care upper digit lower digit 70 3 4 figure 2.3 register data formats
rev. 4.00, 05/03, page 27 of 562 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. the h8/300l cpu can access word data stored in memory (mov.w instruction), but the word data must always begin at an even address. if word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. the same applies to instruction codes. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack ccr: condition code register note: ignored on return * figure 2.4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored.
rev. 4.00, 05/03, page 28 of 562 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2.1. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @Crn 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register directrn: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. 2. register indirect@rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement@(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even.
rev. 4.00, 05/03, page 29 of 562 4. register indirect with post-increment or pre-decrement@rn+ or @Crn: ? register indirect with post-increment@rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. ? register indirect with pre-decrement@Crn the @Crn mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address@aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate#xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative@(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is C126 to +128 bytes (C63 to +64 words) from the current address. the displacement should be an even number. 8. memory indirect@@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see section 3.3, interrupts, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the
rev. 4.00, 05/03, page 30 of 562 address preceding the specified address. see section 2.3.2, memory data formats, for further information. 2.4.2 effective address calculation table 2.2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. register indirect (1) (bset, bclr, bnot, and btst instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand.
rev. 4.00, 05/03, page 31 of 562 table 2.2 effective address calculation addressing mode and instruction format op rm 76 3 40 15 no. effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn register indirect, @rn contents (16 bits) of register indicated by rm 0 15 register indirect with displacement, @(d:16, rn) op rm rn 87 3 40 15 op rm 76 3 40 15 disp op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @ rn 2 3 4 incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 30 rn 30 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm
rev. 4.00, 05/03, page 32 of 562 addressing mode and instruction format no. effective address calculation method effective address (ea) 5 absolute address @aa:8 operand is 1- or 2-byte immediate data @aa:16 op 87 0 15 op 0 15 imm op disp 70 15 program-counter relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs hff 87 0 15 0 15 abs op #xx:16 op 87 0 15 imm immediate #xx:8 8 sign extension disp
rev. 4.00, 05/03, page 33 of 562 addressing mode and instruction format no. effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h00 87 0 15 notation: rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address abs
rev. 4.00, 05/03, page 34 of 562 2.5 instruction set the h8/300l series can use a total of 55 instructions, which are grouped by function in table 2.3. table 2.3 instruction set function instructions number data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: * 1 push rn is equivalent to mov.w rn, @Csp. pop rn is equivalent to mov.w @sp+, rn. the same applies to the machine language. * 2 bcc is a conditional branch instruction in which cc represents a condition code. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next.
rev. 4.00, 05/03, page 35 of 562 notation rd general register (destination) rs general register (source) rn general register (ead), destination operand (eas), source operand ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication division and logical or logical exclusive or logical move ~ logical negation (logical complement) :3 3-bit length :8 8-bit length :16 16-bit length ( ), < > contents of operand indicated by effective address
rev. 4.00, 05/03, page 36 of 562 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:16, @Crn, and @rn+ addressing modes are available for word data. the @aa:8 addressing mode is available for byte data only. the @Cr7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. push w rn @Csp pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @Csp. notes: * size: operand size b: byte w: word certain precautions are required in data access. see section 2.9.1, notes on data access, for details.
rev. 4.00, 05/03, page 37 of 562 15 0 87 op rm rn mov rm rn 15 0 87 op rm rn @rm rn 15 0 87 op rm rn @(d:16, rm) rn disp 15 0 87 op rm rn @rm+ rn, or rn @ rm 15 0 87 op rn abs @aa:8 rn 15 0 87 op rn @aa:16 rn abs 15 0 87 op rn imm #xx:8 rn 15 0 87 op rn #xx:16 rn imm 15 0 87 op rn push, pop notation: op: rm, rn: disp: abs: imm: operation field register field displacement absolute address immediate data @sp+ rn, or rn @ sp 111 figure 2.5 data transfer instruction codes
rev. 4.00, 05/03, page 38 of 562 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs rd, rd + #imm rd performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc dec b rd 1 rd increments or decrements a general register by 1. adds subs w rd 1 rd, rd 2 rd adds or subtracts 1 or 2 to or from a general register daa das b rd decimal adjust rd decimal-adjusts (adjusts to 4-bit bcd) an addition or subtraction result in a general register by referring to the ccr mulxu b rd rs rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result divxu b rd rs rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and indicates the result in the ccr. word data can be compared only between two general registers. neg b 0 C rd rd obtains the twos complement (arithmetic complement) of data in a general register notes: * size: operand size b: byte w: word
rev. 4.00, 05/03, page 39 of 562 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. table 2.6 logic operation instructions instruction size * function and b rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data or b rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data xor b rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data not b ~ rd rd obtains the ones complement (logical complement) of general register contents notes: * size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift rd performs an arithmetic shift operation on general register contents shll shlr b rd shift rd performs a logical shift operation on general register contents rotl rotr b rd rotate rd rotates general register contents rotxl rotxr b rd rotate through carry rd rotates general register contents through the c (carry) bit notes: * size: operand size b: byte
rev. 4.00, 05/03, page 40 of 562 figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) notation: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes
rev. 4.00, 05/03, page 41 of 562 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ~ ( of ) ( of ) inverts a specified bit in a general register or memory. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ~ ( of ) z tests a specified bit in a general register or memory and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band b c ( of ) c ands the c flag with a specified bit in a general register or memory, and stores the result in the c flag. biand b c [~ ( of )] c ands the c flag with the inverse of a specified bit in a general register or memory, and stores the result in the c flag. the bit number is specified by 3-bit immediate data. bor b c ( of ) c ors the c flag with a specified bit in a general register or memory, and stores the result in the c flag. bior b c [~ ( of )] c ors the c flag with the inverse of a specified bit in a general register or memory, and stores the result in the c flag. the bit number is specified by 3-bit immediate data. notes: * size: operand size b: byte
rev. 4.00, 05/03, page 42 of 562 instruction size * function bxor b c ( of ) c xors the c flag with a specified bit in a general register or memory, and stores the result in the c flag. bixor b c [~( of )] c xors the c flag with the inverse of a specified bit in a general register or memory, and stores the result in the c flag. the bit number is specified by 3-bit immediate data. bld b ( of ) c copies a specified bit in a general register or memory to the c flag. bild b ~ ( of ) c copies the inverse of a specified bit in a general register or memory to the c flag. the bit number is specified by 3-bit immediate data. bst b c ( of ) copies the c flag to a specified bit in a general register or memory. bist b ~ c ( of ) copies the inverse of the c flag to a specified bit in a general register or memory. the bit number is specified by 3-bit immediate data. notes: * size: operand size b: byte certain precautions are required in bit manipulation. see section 2.9.2, notes on bit manipulation, for details.
rev. 4.00, 05/03, page 43 of 562 15 0 87 op imm rn operand: bit no.: notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes
rev. 4.00, 05/03, page 44 of 562 notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont)
rev. 4.00, 05/03, page 45 of 562 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc branches to the designated address if condition cc is true. the branching conditions are given below. mnemonicdescription condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp branches unconditionally to a specified address bsr branches to a subroutine at a specified address jsr branches to a subroutine at a specified address rts returns from a subroutine
rev. 4.00, 05/03, page 46 of 562 notation: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes
rev. 4.00, 05/03, page 47 of 562 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte returns from an exception-handling routine sleep causes a transition from active mode to a power-down mode. see section 5, power-down modes, for details. ldc b rs ccr, #imm ccr moves immediate data or general register contents to the condition code register stc b ccr rd copies the condition code register to a specified general register andc b ccr #imm ccr logically ands the condition code register with immediate data orc b ccr #imm ccr logically ors the condition code register with immediate data xorc b ccr #imm ccr logically exclusive-ors the condition code register with immediate data nop pc + 2 pc only increments the program counter notes: * size: operand size b: byte
rev. 4.00, 05/03, page 48 of 562 notation: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes 2.5.8 block data transfer instruction table 2.11 describes the block data transfer instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov if r4l 0 then repeat @r5+ @r6+ r4l C 1 r4l until r4l = 0 else next; block transfer instruction. transfers the number of data bytes specified by r4l from locations starting at the address indicated by r5 to locations starting at the address indicated by r6. after the transfer, the next instruction is executed. certain precautions are required in using the eepmov instruction. see section 2.9.3, notes on use of the eepmov instruction, for details.
rev. 4.00, 05/03, page 49 of 562 notation: op: operation field 15 0 87 op op figure 2.10 block data transfer instruction code
rev. 4.00, 05/03, page 50 of 562 2.6 basic operational timing cpu operation is synchronized by a system clock ( ) or a subclock ( sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.11 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) or sub figure 2.11 on-chip memory access cycle
rev. 4.00, 05/03, page 51 of 562 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. figures 2.12 and 2.13 show the on-chip peripheral module access cycle. two-state access to on-chip peripheral modules t 1 state bus cycle t 2 state or sub internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) figure 2.12 on-chip peripheral module access cycle (2-state access)
rev. 4.00, 05/03, page 52 of 562 three-state access to on-chip peripheral modules t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data or sub figure 2.13 on-chip peripheral module access cycle (3-state access)
rev. 4.00, 05/03, page 53 of 562 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2.14. figure 2.15 shows the state transitions. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode active (medium speed) mode subactive mode sleep (high-speed) mode standby mode watch mode subsleep mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized note: see section 5, power-down modes, for details on the modes and their transitions. sleep (medium-speed) mode figure 2.14 cpu operation states
rev. 4.00, 05/03, page 54 of 562 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source occurs reset occurs interrupt source occurs exception- handling complete reset occurs figure 2.15 state transitions 2.7.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. see section 5, power-down modes for details on these modes. 2.7.3 program halt state in the program halt state there are five modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. see section 5, power-down modes for details on these modes. 2.7.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see section 3.3, interrupts.
rev. 4.00, 05/03, page 55 of 562 2.8 memory map 2.8.1 memory map the memory map of the h8/38024 and h8/38024s are shown in figure 2.16(1), that of the h8/38023 and h8/38023s in figure 2.16(2), that of the h8/38022 and h8/38022s in figure 2.16(3), that of the h8/38021 and h8/38021s in figure 2.16(4), and that of the h8/38020 and h8/38020s in figure 2.16(5). h0000 h0029 h002a h7fff h7000 hf020 hf02b hf740 hf74f hfb80 hfb7f hff7f hff80 hffff interrupt vector area user area (1 kbyte) on-chip rom 32 kbytes (32768 bytes) 1024 bytes internal i/o register (128 bytes) (workarea for reprogramming flash memory: 1 kbyte) * 2 internal i/o register not used firmware for on-chip emulator * 1 hf780 not used not used lcd ram (16 bytes) h0000 h0029 h002a h7fff hf740 hf74f hfb80 hff7f hff80 hffff interrupt vector area hd64f38024, hd64f38024r (flash memory version) hd64338024 (mask rom version) hd64338024s (mask rom version) hd64738024 (prom version) on-chip rom 32 kbytes (32768 bytes) 1024 bytes on-chip ram internal i/o register (128 bytes) not used not used lcd ram (16 bytes) on-chip ram (2 kbytes) notes: * 1 not available to the user if the on-chip emulator is used. * 2 used by the programming control program when programming flash memory. also, not available to the user if the on-chip emulator is used. figure 2.16(1) h8/38024 and h8/38024s memory map
rev. 4.00, 05/03, page 56 of 562 h0000 h0029 h002a h5fff hf740 hf74f hfb80 hff7f hff80 hffff interrupt vector area on-chip rom 24 kbytes (24576 bytes) 1024 bytes on-chip ram internal i/o registers (128 bytes) not used not used lcd ram (16 bytes) figure 2.16(2) h8/38023 and h8/38023s memory map
rev. 4.00, 05/03, page 57 of 562 h0000 h0029 h002a h3fff hf740 hf74f hfb80 hff7f hff80 hffff interrupt vector area on-chip rom 16 kbytes (16384 bytes) 1024 bytes on-chip ram internal i/o registers (128 bytes) not used not used lcd ram (16 bytes) figure 2.16(3) h8/38022 and h8/38022s memory map
rev. 4.00, 05/03, page 58 of 562 h0000 h0029 h002a h2fff hf740 hf74f hfd80 hff7f hff80 hffff interrupt vector area on-chip rom 12 kbytes (12288 bytes) 512 bytes on-chip ram internal i/o registers (128 bytes) not used not used lcd ram (16 bytes) figure 2.16(4) h8/38021 and h8/38021s memory map
rev. 4.00, 05/03, page 59 of 562 h0000 h0029 h002a h1fff hf740 hf74f hfd80 hff7f hff80 hffff interrupt vector area on-chip rom 8 kbytes (8192 bytes) 512 bytes on-chip ram internal i/o registers (128 bytes) not used not used lcd ram (16 bytes) figure 2.16(5) h8/38020 and h8/38020s memory map
rev. 4.00, 05/03, page 60 of 562 2.9 application notes 2.9.1 notes on data access 1. access to empty areas: the address space of the h8/300l cpu includes empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. data transfer from cpu to empty area: the transferred data will be lost. this action may also cause the cpu to misoperate. data transfer from empty area to cpu: unpredictable data is transferred. 2. access to internal i/o registers: internal data transfer to or from on-chip modules other than the rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: unpredictable data will be written to lower part of cpu register. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas. figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed.
rev. 4.00, 05/03, page 61 of 562 interrupt vector area (42 bytes) on-chip rom 32 kbytes user area internal ram not used lcd ram (16 bytes) internal i/o registers (128 bytes) (1-kbyte work area for flash memory programming) access word byte 2 not used not used 2 2 3 2 3 2 2 states 1024 bytes hffa8 to hffaf h0000 h0029 h002a h7fff hf740 hf020 hf02b hf74f hf780 hfb7f hfb80 hff7f hff80 hffff notes: * 1 * 3 * 3 the example of the h8/38024 is shown here. * 1 this address is h7fff in the h8/38024 and h8/38024s (32-kbyte on-chip rom), h5fff in the h8/38023 and h8/38023s (24-kbyte on-chip rom), h3fff in the h8/38022 and h8/38022s (16-kbyte on-chip rom), h2fff in the h8/38021 and h8/38021s (12-kbyte on- chip rom), h1fff in the h8/38020 and h8/38020s (8-kbyte on-chip rom). * 2 this address is hfd80 in the h8/38021, h8/38021s, h8/38020, and h8/38020s (512 bytes of on-chip ram). * 3 internal i/o registers with addresses from hf020 to hf02b and on-chip ram with addresses from hf780 to hfb7f are installed on the hd64f38024 and hd64f38024r only. attempting to access these addresses on products other than the hd64f38024 and hd64f38024r will result in access to an empty area. hff98 to hff9f 2 internal i/o registers 2 * 2 figure 2.17 data size and number of states for access to and from on-chip peripheral modules
rev. 4.00, 05/03, page 62 of 562 2.9.2 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an i/o port. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address 1. bit manipulation in two registers assigned to the same address example 1: timer load register and timer counter figure 2.18 shows an example in which two timer registers share the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. order of operation operation 1 read timer counter data is read (one byte) 2 modify the cpu modifies (sets or resets) the bit designated in the instruction 3 write the altered byte data is written to the timer load register the timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. read write count clock timer counter timer load register reload internal data bus figure 2.18 timer configuration example
rev. 4.00, 05/03, page 63 of 562 example 2: bset instruction executed designating port 3 p3 7 and p3 6 are designated as input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 1 , are output pins and output low-level signals. in this example, the bset instruction is used to change pin p3 0 to high-level output. [a: prior to executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 [b: bset instruction executed] bset #0 , @pdr3 the bset instruction is executed designating port 3. [c: after executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr300111111 pdr3 0 100000 1 [d: explanation of how bset operates] when the bset instruction is executed, first the cpu reads port 3. since p3 7 and p3 6 are input pins, the cpu reads the pin states (low-level and high-level input). p3 5 to p3 0 are output pins, so the cpu reads the value in pdr3. in this example pdr3 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr3 data to h'41. finally, the cpu writes this value (h'41) to pdr3, completing execution of bset. as a result of this operation, bit 0 in pdr3 becomes 1, and p3 0 outputs a high-level signal. however, bits 7 and 6 of pdr3 end up with different values. to avoid this problem, store a copy of the pdr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr3.
rev. 4.00, 05/03, page 64 of 562 [a: prior to executing bset] mov. b #80, r0l the pdr3 value (h'80) is written to a work area in memory mov. b r0l, @ram0 (ram0) as well as to pdr3 mov. b r0l, @pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 ram010000000 [b: bset instruction executed] bset #0 , @ram0 the bset instruction is executed designating the pdr3 work area (ram0). [c: after executing bset] mov. b @ram0, r0l the work area (ram0) value is written to pdr3. mov. b r0l, @pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr300111111 pdr31000000 1 ram01000000 1
rev. 4.00, 05/03, page 65 of 562 2. bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 3 control register pcr3 as in the examples above, p3 7 and p3 6 are input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p3 0 to an input port. it is assumed that a high-level signal will be input to this input pin. [a: prior to executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 [b: bclr instruction executed] bclr #0 , @pcr3 the bclr instruction is executed designating pcr3. [c: after executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output output output output output output output output input pin state low level high level low level low level low level low level low level high level pcr3 1 111111 0 pdr310000000 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads pcr3. since pcr3 is a write-only register, the cpu reads a value of h'ff, even though the pcr3 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, this value (h'fe) is written to pcr3 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr3 becomes 0, making p3 0 an input port. however, bits 7 and 6 in pcr3 change to 1, so that p3 7 and p3 6 change from input pins to output pins. to avoid this problem, store a copy of the pcr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pcr3.
rev. 4.00, 05/03, page 66 of 562 [a: prior to executing bclr] mov. b #3f, r0l the pcr3 value (h'3f) is written to a work area in memory mov. b r0l, @ram0 (ram0) as well as to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr300111111 pdr310000000 ram000111111 [b: bclr instruction executed] bclr #0 , @ram0 the bclr instruction is executed designating the pcr3 work area (ram0). [c: after executing bclr] mov. b @ram0, r0l the work area (ram0) value is written to pcr3. mov. b r0l, @pcr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr30011111 0 pdr310000000 ram00011111 0 table 2.12 lists the pairs of registers that share identical addresses. table 2.13 lists the registers that contain write-only bits.
rev. 4.00, 05/03, page 67 of 562 table 2.12 registers with shared addresses register name abbreviation address timer counter c/timer load register c tcc/tlc h'ffb5 port data register 1 * pdr1 h'ffd4 port data register 3 * pdr3 h'ffd6 port data register 4 * pdr4 h'ffd7 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb port data register a * pdra h'ffdd note: * port data registers have the same addresses as input pins. table 2.13 registers with write-only bits register name abbreviation address port control register 1 pcr1 h'ffe4 port control register 3 pcr3 h'ffe6 port control register 4 pcr4 h'ffe7 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb port control register a pcra h'ffed timer control register f tcrf h'ffb6 pwm1 control register pwcr1 h'ffd0 pwm1 data register u pwdru1 h'ffd1 pwm1 data register l pwdrl1 h'ffd2 pwm2 control register pwcr2 h'ffcd pwm2 data register u pwdru2 h'ffce pwm2 data register l pwdrl2 h'ffcf event counter pwm data register h ecpwdrh h'ff8e event counter pwm data register l ecpwdrl h'ff8f
rev. 4.00, 05/03, page 68 of 562 2.9.3 notes on use of the eepmov instruction ? the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. r6 r6 + r4l r5 r5 + r4l ? when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. hffff not allowed r6 r6 + r4l r5 r5 + r4l
rev. 4.00, 05/03, page 69 of 562 section 3 exception handling 3.1 overview exception handling is performed in the h8/38024 group when a reset or interrupt occurs. table 3.1 shows the priorities of these two types of exception handling. table 3.1 exception handling types and priorities priority exception source time of start of exception handling high reset exception handling starts as soon as the reset state is cleared low interrupt when an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 reset 3.2.1 overview a reset is the highest-priority exception. the internal state of the cpu and the registers of the on- chip peripheral modules are initialized. 3.2.2 reset sequence as soon as the res pin goes low, all processing is stopped and the chip enters the reset state. to make sure the chip is reset properly, observe the following precautions. ? at power on: hold the res pin low until the clock pulse generator output stabilizes. ? resetting during operation: hold the res pin low for at least 10 system clock cycles. reset exception handling takes place as follows. ? the cpu internal state and the registers of on-chip peripheral modules are initialized, with the i bit of the condition code register (ccr) set to 1. ? the pc is loaded from the reset exception handling vector address (h'0000 to h'0001), after which the program starts executing from the address indicated in pc.
rev. 4.00, 05/03, page 70 of 562 when system power is turned on or off, the res pin should be held low. figure 3.1 shows the reset sequence starting from res input. vector fetch internal address bus internal read signal internal write signal internal data bus (16-bit) internal processing program initial instruction prefetch (1) reset exception handling vector address (h0000) (2) program start address (3) first instruction of program (2) (3) (2) (1) reset cleared figure 3.1 reset sequence 3.2.3 interrupt immediately after reset after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.w #xx: 16, sp).
rev. 4.00, 05/03, page 71 of 562 3.3 interrupts 3.3.1 overview the interrupt sources include 13 external interrupts (wkp 7 to wkp 0 , irq 4 , irq 3 , irq 1 , irq 0 , irqaec) and 9 internal interrupts from on-chip peripheral modules. table 3.2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features: ? internal and external interrupts can be masked by the i bit in ccr. when the i bit is set to 1, interrupt request flags can be set but the interrupts are not accepted. ? irq 4 , irq 3 , irq 1 , irq 0 , and wkp 7 to wkp 0 can be set to either rising edge sensing or falling edge sensing, and irqaec can be set to either rising edge sensing, falling edge sensing, or both edge sensing.
rev. 4.00, 05/03, page 72 of 562 table 3.2 interrupt sources and their priorities interrupt source interrupt vector number vector address priority res watchdog timer reset 0 h'0000 to h'0001 high irq 0 irq 0 4 h'0008 to h'0009 irq 1 irq 1 5 h'000a to h'000b irqaec irqaec 6 h'000c to h'000d irq 3 irq 3 7 h'000e to h'000f irq 4 irq 4 8 h'0010 to h'0011 wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 wkp 0 wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 9 h'0012 to h'0013 timer a timer a overflow 11 h'0016 to h'0017 asynchronous event counter asynchronous event counter overflow 12 h'0018 to h'0019 timer c timer c overflow or underflow 13 h'001a to h'001b timer fltimer fl compare match timer fl overflow 14 h'001c to h'001d timer fh timer fh compare match timer fh overflow 15 h'001e to h'001f timer g timer g input capture timer g overflow 16 h'0020 to h'0021 sci3 sci3 transmit end sci3 transmit data empty sci3 receive data full sci3 overrun error sci3 framing error sci3 parity error 18 h'0024 to h'0025 a/d a/d conversion end 19 h'0026 to h'0027 (sleep instruction executed) direct transfer 20 h'0028 to h'0029 low note: vector addresses h'0002 to h'0007, h'0014 to h'0015, and h'0022 to h'0023 are reserved and cannot be used.
rev. 4.00, 05/03, page 73 of 562 3.3.2 interrupt control registers table 3.3 lists the registers that control interrupts. table 3.3 interrupt control registers name abbreviation r/w initial value address irq edge select register iegr r/w h'fff2 interrupt enable register 1 ienr1 r/w h'fff3 interrupt enable register 2 ienr2 r/w h'fff4 interrupt request register 1 irr1 r/w * h'fff6 interrupt request register 2 irr2 r/w * h'fff7 wakeup interrupt request register iwpr r/w * h'00 h'fff9 wakeup edge select register wegr r/w h'00 h'ff90 note: * write is enabled only for writing of 0 to clear a flag. 1. irq edge select register (iegr) bit initial value read/write 7 1 6 1 5 1 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 w 1 ieg1 0 r/w iegr is an 8-bit read/write register used to designate whether pins irq 4 , irq 3 , irq 1 , and irq 0 are set to rising edge sensing or falling edge sensing. for the irqaec pin edge sensing specifications, see section 9.7, asynchronous event counter (aec). bits 7 to 5: reserved bits bits 7 to 5 are reserved: they are always read as 1 and cannot be modified. bit 4: irq 4 edge select (ieg4) bit 4 selects the input sensing of the irq 4 pin and adtrg pin. bit 4 ieg4 description 0 falling edge of irq 4 and adtrg pin input is detected (initial value) 1 rising edge of irq 4 and adtrg pin input is detected
rev. 4.00, 05/03, page 74 of 562 bit 3: irq 3 edge select (ieg3) bit 3 selects the input sensing of the irq 3 pin and tmif pin. bit 3 ieg3 description 0 falling edge of irq 3 and tmif pin input is detected (initial value) 1 rising edge of irq 3 and tmif pin input is detected bit 2: reserved bit bit 2 is reserved: it can only be written with 0. bit 1: irq 1 edge select (ieg1) bit 1 selects the input sensing of the irq 1 pin and tmic pin. bit 1 ieg1 description 0 falling edge of irq 1 and tmic pin input is detected (initial value) 1 rising edge of irq 1 and tmic pin input is detected bit 0: irq 0 edge select (ieg0) bit 0 selects the input sensing of pin irq 0 . bit 0 ieg0 description 0 falling edge of irq 0 pin input is detected (initial value) 1 rising edge of irq 0 pin input is detected 2. interrupt enable register 1 (ienr1) bit initial value read/write 7 ienta 0 r/w 6 w 5 ienwp 0 r/w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ienec2 0 r/w 1 ien1 0 r/w ienr1 is an 8-bit read/write register that enables or disables interrupt requests.
rev. 4.00, 05/03, page 75 of 562 bit 7: timer a interrupt enable (ienta) bit 7 enables or disables timer a overflow interrupt requests. bit 7 ienta description 0 disables timer a interrupt requests (initial value) 1 enables timer a interrupt requests bit 6: reserved bit bit 6 is reserved: it can only be written with 0. bit 5: wakeup interrupt enable (ienwp) bit 5 enables or disables wkp 7 to wkp 0 interrupt requests. bit 5 ienwp description 0 disables wkp 7 to wkp 0 interrupt requests (initial value) 1 enables wkp 7 to wkp 0 interrupt requests bits 4 and 3: irq 4 and irq 3 interrupt enable (ien4 and ien3) bits 4 and 3 enable or disable irq 4 and irq 3 interrupt requests. bit n ienn description 0 disables interrupt requests from pin irqn (initial value) 1 enables interrupt requests from pin irqn (n = 4, 3) bit 2: irqaec interrupt enable (ienec2) bit 2 enables or disables irqaec interrupt requests. bit 2 ienec2 description 0 disables irqaec interrupt requests (initial value) 1 enables irqaec interrupt requests
rev. 4.00, 05/03, page 76 of 562 bits 1 and 0: irq 1 and irq 0 interrupt enable (ien1 and ien0) bits 1 and 0 enable or disable irq 1 and irq 0 interrupt requests. bit n ienn description 0 disables interrupt requests from pin irqn (initial value) 1 enables interrupt requests from pin irqn (n = 1 or 0) 3. interrupt enable register 2 (ienr2) bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 w 4 ientg 0 r/w 3 ientfh 0 r/w 0 ienec 0 r/w 2 ientfl 0 r/w 1 ientc 0 r/w ienr2 is an 8-bit read/write register that enables or disables interrupt requests. bit 7: direct transfer interrupt enable (iendt) bit 7 enables or disables direct transfer interrupt requests. bit 7 iendt description 0 disables direct transfer interrupt requests (initial value) 1 enables direct transfer interrupt requests bit 6: a/d converter interrupt enable (ienad) bit 6 enables or disables a/d converter interrupt requests. bit 6 ienad description 0 disables a/d converter interrupt requests (initial value) 1 enables a/d converter interrupt requests bit 5: reserved bit bit 5 is reserved bit: it can only be written with 0.
rev. 4.00, 05/03, page 77 of 562 bit 4: timer g interrupt enable (ientg) bit 4 enables or disables timer g input capture or overflow interrupt requests. bit 4 ientg description 0 disables timer g interrupt requests (initial value) 1 enables timer g interrupt requests bit 3: timer fh interrupt enable (ientfh) bit 3 enables or disables timer fh compare match and overflow interrupt requests. bit 3 ientfh description 0 disables timer fh interrupt requests (initial value) 1 enables timer fh interrupt requests bit 2: timer fl interrupt enable (ientfl) bit 2 enables or disables timer fl compare match and overflow interrupt requests. bit 2 ientfl description 0 disables timer fl interrupt requests (initial value) 1 enables timer fl interrupt requests bit 1: timer c interrupt enable (ientc) bit 1 enables or disables timer c overflow and underflow interrupt requests. bit 1 ientc description 0 disables timer c interrupt requests (initial value) 1 enables timer c interrupt requests
rev. 4.00, 05/03, page 78 of 562 bit 0: asynchronous event counter interrupt enable (ienec) bit 0 enables or disables asynchronous event counter interrupt requests. bit 0 ienec description 0 disables asynchronous event counter interrupt requests (initial value) 1 enables asynchronous event counter interrupt requests for details of sci3 interrupt control, see section 10.2.6 serial control register 3 (scr3). 4. interrupt request register 1 (irr1) bit initial value read/write 7 irrta 0 r/(w) * 6 w 5 1 4 irri4 0 r/(w) * 3 irri3 0 r/(w) * 0 irri0 0 r/(w) * 2 irrec2 0 r/(w) * 1 irri1 0 r/(w) * note: * only a write of 0 for flag clearing is possible irr1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer a, irqaec, irq 4 , irq 3 , irq 1 , or irq 0 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: timer a interrupt request flag (irrta) bit 7 irrta description 0 clearing conditions: (initial value) when irrta = 1, it is cleared by writing 0 1 setting conditions: when the timer a counter value overflows from h'ff to h'00 bit 6: reserved bit bit 6 is reserved; it can only be written with 0. bit 5: reserved bit bit 5 is reserved; it is always read as 1 and cannot be modified.
rev. 4.00, 05/03, page 79 of 562 bits 4 and 3 : irq 4 and irq 3 interrupt request flags (irri4 and irri3) bit n irrin description 0 clearing conditions: (initial value) when irrin = 1, it is cleared by writing 0 1 setting conditions: when pin irqn is designated for interrupt input and the designated signal edge is input (n = 4 or 3) bit 2: irqaec interrupt request flag (irrec2) bit 2 irrec2 description 0 clearing conditions: (initial value) when irrec2 = 1, it is cleared by writing 0 1 setting conditions: when pin irqaec is designated for interrupt input and the designated signal edge is input bits 1 and 0: irq 1 and irq 0 interrupt request flags (irri1 and irri0) bit n irrin description 0 clearing conditions: (initial value) when irrin = 1, it is cleared by writing 0 1 setting conditions: when pin irqn is designated for interrupt input and the designated signal edge is input (n = 1 or 0)
rev. 4.00, 05/03, page 80 of 562 5. interrupt request register 2 (irr2) bit initial value read/write 7 irrdt 0 r/(w) * 6 irrad 0 r/(w) * 5 w 4 irrtg 0 r/(w) * 3 irrtfh 0 r/(w) * 0 irrec 0 r/(w) * 2 irrtfl 0 r/(w) * 1 irrtc 0 r/(w) * note: * only a write of 0 for flag clearing is possible irr2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, a/d converter, timer g, timer fh, timer fl, timer c, or asynchronous event counter interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit 7: direct transfer interrupt request flag (irrdt) bit 7 irrdt description 0 clearing conditions: (initial value) when irrdt = 1, it is cleared by writing 0 1 setting conditions: when a direct transfer is made by executing a sleep instruction while dton = 1 in syscr2 bit 6: a/d converter interrupt request flag (irrad) bit 6 irrad description 0 clearing conditions: (initial value) when irrad = 1, it is cleared by writing 0 1 setting conditions: when a/d conversion is completed and adsf is cleared to 0 in adsr bit 5: reserved bit bit 5 is reserved: it can only be written with 0.
rev. 4.00, 05/03, page 81 of 562 bit 4: timer g interrupt request flag (irrtg) bit 4 irrtg description 0 clearing conditions: (initial value) when irrtg = 1, it is cleared by writing 0 1 setting conditions: when the tmig pin is designated for tmig input and the designated signal edge is input, and when tcg overflows while ovie is set to 1 in tmg bit 3: timer fh interrupt request flag (irrtfh) bit 3 irrtfh description 0 clearing conditions: (initial value) when irrtfh = 1, it is cleared by writing 0 1 setting conditions: when tcfh and ocrfh match in 8-bit timer mode, or when tcf (tcfl, tcfh) and ocrf (ocrfl, ocrfh) match in 16-bit timer mode bit 2: timer fl interrupt request flag (irrtfl) bit 2 irrtfl description 0 clearing conditions: (initial value) when irrtfl = 1, it is cleared by writing 0 1 setting conditions: when tcfl and ocrfl match in 8-bit timer mode bit 1: timer c interrupt request flag (irrtc) bit 1 irrtc description 0 clearing conditions: (initial value) when irrtc = 1, it is cleared by writing 0 1 setting conditions: when the timer c counter value overflows (from h'ff to h'00) or underflows (from h'00 to h'ff)
rev. 4.00, 05/03, page 82 of 562 bit 0: asynchronous event counter interrupt request flag (irrec) bit 0 irrec description 0 clearing conditions: (initial value) when irrec = 1, it is cleared by writing 0 1 setting conditions: when ech overflows in 16-bit counter mode, or ech or ecl overflows in 8-bit counter mode 6. wakeup interrupt request register (iwpr) bit initial value read/write 7 iwpf7 0 r/(w) * 6 iwpf6 0 r/(w) * 5 iwpf5 0 r/(w) * 4 iwpf4 0 r/(w) * 3 iwpf3 0 r/(w) * 0 iwpf0 0 r/(w) * 2 iwpf2 0 r/(w) * 1 iwpf1 0 r/(w) * note: * only a write of 0 for flag clearing is possible iwpr is an 8-bit read/write register containing wakeup interrupt request flags. when one of pins wkp 7 to wkp 0 is designated for wakeup input and a rising or falling edge is input at that pin, the corresponding flag in iwpr is set to 1. a flag is not cleared automatically when the corresponding interrupt is accepted. flags must be cleared by writing 0. bits 7 to 0: wakeup interrupt request flags (iwpf7 to iwpf0) bit n iwpfn description 0 clearing conditions: (initial value) when iwpfn= 1, it is cleared by writing 0 1 setting conditions: when pin wkp n is designated for wakeup input and a rising or falling edge is input at that pin (n = 7 to 0)
rev. 4.00, 05/03, page 83 of 562 7. wakeup edge select register (wegr) bit initial value read/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 4 wkegs4 0 r/w 3 wkegs3 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w wegr is an 8-bit read/write register that specifies rising or falling edge sensing for pins wkp n. wegr is initialized to h'00 by a reset. bit n: wkp n edge select (wkegsn) bit n selects wkp n pin input sensing. bit n wkegsn description 0 wkp n pin falling edge detected (initial value) 1 wkp n pin rising edge detected (n = 7 to 0) 3.3.3 external interrupts there are 13 external interrupts: wkp7 to wkp0, irq4, irq3, irq1, irq0, and irqaec. 1. interrupts wkp 7 to wkp 0 interrupts wkp7 to wkp0 are requested by either rising or falling edge input to pins wkp 7 to wkp 0 . when these pins are designated as pins wkp 7 to wkp 0 in port mode register 5 and a rising or falling edge is input, the corresponding bit in iwpr is set to 1, requesting an interrupt. recognition of wakeup interrupt requests can be disabled by clearing the ienwp bit to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when wkp7 to wkp0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector number 9 is assigned to interrupts wkp7 to wkp0. all eight interrupt sources have the same vector number, so the interrupt-handling routine must discriminate the interrupt source.
rev. 4.00, 05/03, page 84 of 562 2. interrupts irq 4 , irq 3 , irq 1 and irq 0 interrupts irq4, irq3, irq1, and irq0 are requested by input signals to pins irq 4 , irq 3 , irq 1 , and irq 0 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg4, ieg3, ieg1, and ieg0 in iegr. when these pins are designated as pins irq 4 , irq 3 , irq 1 , and irq 0 in port mode register b, 2, and 1 and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. recognition of these interrupt requests can be disabled individually by clearing bits ien4, ien3, ien1, and ien0 to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when irq4, irq3, irq1, and irq0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector numbers 8, 7, 5, and 4 are assigned to interrupts irq4, irq3, irq1, and irq0. the order of priority is from irq0 (high) to irq4 (low). table 3.2 gives details. 3. irqaec interrupt the irqaec interrupt is requested by an input signal to pin irqaec and iecpwm (output of pwm for aec). when the irqaec input pin is to be used as an external interrupt, set ecpwme in aegsr to 0. this interrupt is detected by rising edge, falling edge, or both edge sensing, depending on the settings of bits aiegs1 and aiegs0 in aegsr. when bit ienec2 in ienr1 is 1 and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. when irqaec interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector number 6 is assigned to the irqaec interrupt exception handling. table 3.2 gives details. 3.3.4 internal interrupts there are 9 internal interrupts that can be requested by the on-chip peripheral modules. when a peripheral module requests an interrupt, the corresponding bit in irr1 or irr2 is set to 1. recognition of individual interrupt requests can be disabled by clearing the corresponding bit in ienr1 or ienr2. all these interrupts can be masked by setting the i bit to 1 in ccr. when internal interrupt handling is initiated, the i bit is set to 1 in ccr. vector numbers from 20 to 18 and 16 to 11 are assigned to these interrupts. table 3.2 shows the order of priority of interrupts from on-chip peripheral modules.
rev. 4.00, 05/03, page 85 of 562 3.3.5 interrupt operations interrupts are controlled by an interrupt controller. figure 3.2 shows a block diagram of the interrupt controller. figure 3.3 shows the flow up to interrupt acceptance. interrupt controller priority decision logic interrupt request ccr (cpu) i external or internal interrupts external interrupts or internal interrupt enable signals figure 3.2 block diagram of interrupt controller interrupt operation is described as follows. ? when an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. ? when the interrupt controller receives an interrupt request, it sets the interrupt request flag. ? from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (refer to table 3.2 for a list of interrupt priorities.) ? the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. ? if the interrupt request is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.4. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.
rev. 4.00, 05/03, page 86 of 562 ? the i bit of ccr is set to 1, masking further interrupts. ? the vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. notes: 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed.
rev. 4.00, 05/03, page 87 of 562 pc contents saved ccr contents saved i 1 i = 0 program execution state no yes yes no notation: pc: ccr: i: program counter condition code register i bit of ccr ien0 = 1 no yes iendt = 1 no yes irrdt = 1 no yes branch to interrupt handling routine irri0 = 1 no yes ien1 = 1 no yes irri1 = 1 no yes ien2 = 1 no yes irri2 = 1 figure 3.3 flow up to interrupt acceptance
rev. 4.00, 05/03, page 88 of 562 pc and ccr saved to stack sp (r7) sp 1 sp 2 sp 3 sp 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling notation: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr pc h pc l 1. 2. * pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word access, starting from an even-numbered address. ignored on return. * figure 3.4 stack state after completion of interrupt exception handling figure 3.5 shows a typical interrupt sequence.
rev. 4.00, 05/03, page 89 of 562 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp 2 (6) sp 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.5 interrupt sequence
rev. 4.00, 05/03, page 90 of 562 3.3.6 interrupt response time table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. table 3.4 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 13 15 to 27 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction.
rev. 4.00, 05/03, page 91 of 562 3.4 application notes 3.4.1 notes on stack area use when word data is accessed in the lsi, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @Csp) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3.6. pc pc r1l pc sp sp sp hfefc hfefd hfeff h l l mov. b r1l, @ r7 sp set to hfeff stack accessed beyond sp bsr instruction contents of pc are lost h notation: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer figure 3.6 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when rte is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to ccr while the odd address contents are ignored.
rev. 4.00, 05/03, page 92 of 562 3.4.2 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins and when the value of ecpwme in aegsr is rewritten to switch between selection/non-selection of irqaec, the following points should be observed. when an external interrupt pin function is switched by rewriting the port mode register that controls pins irq 4 , irq 3 , irq 1 , irq 0 , wkp 7 to wkp 0 , the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching pin functions. when the value of ecpwme in aegsr that sets selection/non-selection of irqaec is rewritten, the interrupt request flag may be set to 1, even if a valid edge has not arrived on the selected irqaec or iecpwm (pwm output for aec). therefore, be sure to clear the interrupt request flag to 0 after switching the pin function. table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way.
rev. 4.00, 05/03, page 93 of 562 table 3.5 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irr1 irri4 when pmr1 bit irq4 is changed from 0 to 1 while pin irq 4 is low and iegr bit ieg4 = 0. when pmr1 bit irq4 is changed from 1 to 0 while pin irq 4 is low and iegr bit ieg4 = 1. irri3 when pmr1 bit irq3 is changed from 0 to 1 while pin irq 3 is low and iegr bit ieg3 = 0. when pmr1 bit irq3 is changed from 1 to 0 while pin irq 3 is low and iegr bit ieg3 = 1. irrec2 when an edge as designated by aiegs1 and aiegs0 in aegsr is detected because the values on the irqaec pin and of iecpwm at switching are different (e.g., when the rising edge has been selected and ecpwme in aegsr is changed from 1 to 0 while pin irqaec is low and iecpwm = 1). irri1 when pmrb bit irq1 is changed from 0 to 1 while pin irq 1 is low and iegr bit ieg1 = 0. when pmrb bit irq1 is changed from 1 to 0 while pin irq 1 is low and iegr bit ieg1 = 1. irri0 when pmr2 bit irq0 is changed from 0 to 1 while pin irq 0 is low and iegr bit ieg0 = 0. when pmr2 bit irq0 is changed from 1 to 0 while pin irq 0 is low and iegr bit ieg0 = 1. iwpr iwpf7 when pmr5 bit wkp7 is changed from 0 to 1 while pin wkp 7 is low. iwpf6 when pmr5 bit wkp6 is changed from 0 to 1 while pin wkp 6 is low. iwpf5 when pmr5 bit wkp5 is changed from 0 to 1 while pin wkp 5 is low. iwpf4 when pmr5 bit wkp4 is changed from 0 to 1 while pin wkp 4 is low. iwpf3 when pmr5 bit wkp3 is changed from 0 to 1 while pin wkp 3 is low. iwpf2 when pmr5 bit wkp2 is changed from 0 to 1 while pin wkp 2 is low. iwpf1 when pmr5 bit wkp1 is changed from 0 to 1 while pin wkp 1 is low. iwpf0 when pmr5 bit wkp0 is changed from 0 to 1 while pin wkp 0 is low. figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. when switching a pin function, mask the interrupt before setting the bit in the port mode register (or aegsr). after accessing the port mode register (or aegsr), execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag is executed immediately after the port mode register (or aegsr) access without executing an intervening instruction, the flag will not be cleared.
rev. 4.00, 05/03, page 94 of 562 an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. however, the procedure in figure 3.7 is recommended because iecpwm is an internal signal and determining its value is complicated. ccr i bit 1 set port mode register (or aegsr) bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register (or aegsr) bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0 figure 3.7 port mode register (or aegsr) setting and interrupt request flag clearing procedure 3.4.3 method for clearing interrupt request flags use the recommended method, given below when clearing the flags of interrupt request registers (irr1, irr2, iwpr). ? recommended method use a single instruction to clear flags. the bit control instruction and byte-size data transfer instruction can be used. two examples of program code for clearing irri1 (bit 1 of irr1) are given below. bclr #1, @irr1:8 mov.b r1l, @irr1:8 (set the value of r1l to b'11111101) ? example of a malfunction when flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. here is an example in which irri0 is cleared and disabled in the process of clearing irri1 (bit 1 of irr1).
rev. 4.00, 05/03, page 95 of 562 mov.b @irr1:8,r1l ......... irri0 = 0 at this time and.b #b'11111101,r1l ..... here, irri0 = 1 mov.b r1l,@irr1:8 ......... irri0 is cleared to 0 in the above example, it is assumed that an irq0 interrupt is generated while the and.b instruction is executing. the irq0 interrupt is disabled because, although the original objective is clearing irri1, irri0 is also cleared.
rev. 4.00, 05/03, page 96 of 562
rev. 4.00, 05/03, page 97 of 562 section 4 clock pulse generators 4.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 block diagram figure 4.1 shows a block diagram of the clock pulse generators. system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider system clock pulse generator subclock pulse generator prescaler s (13 bits) prescaler w (5 bits) osc osc 1 2 x x 1 2 osc ( f osc ) w w ( f w ) osc /2 w /2 w /8 sub /2 to /8192 w /2 w /4 w /8 to w /128 osc /128 osc /64 osc /32 osc /16 w /4 figure 4.1 block diagram of clock pulse generators 4.1.2 system clock and subclock the basic clock signals that drive the cpu and on-chip peripheral modules are and sub . four of the clock signals have names: is the system clock, sub is the subclock, osc is the oscillator clock, and w is the watch clock. the clock signals available for use by peripheral modules are /2, /4, /8, /16, /32, /64, /128, /256, /512, /1024, /2048, /4096, /8192, w , w /2, w /4, w /8, w /16, w /32, w /64, and w /128. the clock requirements differ from one module to another.
rev. 4.00, 05/03, page 98 of 562 4.2 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. connecting a crystal oscillator figure 4.2 shows a typical method of connecting a crystal oscillator. c 1 c 2 osc 1 osc 2 r = 1 m 20% f r f frequency 4.19 mhz crystal oscillator ndk c 1 , c 2 recommendation value 12 pf 20% figure 4.2 typical connection to crystal oscillator figure 4.3 shows the equivalent circuit of a crystal oscillator. an oscillator having the characteristics given in table 4.1 should be used. c s c 0 r s osc 1 osc 2 l s figure 4.3 equivalent circuit of crystal oscillator table 4.1 crystal oscillator parameters frequency (mhz) 4.193 rs max ( ? ) 100 c 0 max (pf) 16
rev. 4.00, 05/03, page 99 of 562 2. connecting a ceramic oscillator figure 4.4 shows a typical method of connecting a ceramic oscillator. 1 2 c 1 c 2 osc osc r f r = 1 m 20% f frequency 4.0 mhz ceramic oscillator murata c 1 , c 2 recommendation value 30 pf 10% figure 4.4 typical connection to ceramic oscillator 3. notes on board design when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 4.5.) the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . osc osc c 1 c 2 signal a signal b 2 1 to be avoided figure 4.5 board design of oscillator circuit note: the circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. the circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. when using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters.
rev. 4.00, 05/03, page 100 of 562 4. external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 4.6 shows a typical connection. osc 1 osc 2 external clock input open figure 4.6 external clock input (example) frequency oscillator clock ( osc ) duty cycle 45% to 55%
rev. 4.00, 05/03, page 101 of 562 4.3 subclock generator 1. connecting a 32.768 khz/38.4 khz crystal oscillator clock pulses can be supplied to the subclock divider by connecting a 32.768 khz/38.4 khz crystal oscillator, as shown in figure 4.7. follow the same precautions as noted under 3. notes on board design for the system clock in section 4.2. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 frequency 32.768 khz 38.4 khz crystal oscillator nihon denpa kogyo seiko instrument inc. products name mx73p vtc-200 figure 4.7 typical connection to 32.768 khz/38.4 khz crystal oscillator (subclock) figure 4.8 shows the equivalent circuit of the 32.768 khz/38.4 khz crystal oscillator. c s c 0 lr s x 1 x 2 c = 1.5 pf typ r = 14 k typ f = 32.768 khz/38.4 khz 0 s w s figure 4.8 equivalent circuit of 32.768 khz/38.4 khz crystal oscillator
rev. 4.00, 05/03, page 102 of 562 2. pin connection when not using subclock when the subclock is not used, connect pin x 1 to gnd and leave pin x 2 open, as shown in figure 4.9. x x 1 2 gnd open figure 4.9 pin connection when not using subclock 3. external clock input connect the external clock to the x1 pin and leave the x2 pin open, as shown in figure 4.10. x 1 external clock input x 2 open figure 4.10 pin connection when inputting external clock frequency subclock ( w) duty 45% to 55%
rev. 4.00, 05/03, page 103 of 562 4.4 prescalers the h8/38024 group is equipped with two on-chip prescalers having different input clocks (prescaler s and prescaler w). prescaler s is a 13-bit counter using the system clock ( ) as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is a 5-bit counter using a 32.768 khz or 38.4 khz signal divided by 4 ( w /4) as its input clock. its prescaled outputs are used by timer a as a time base for timekeeping. 1. prescaler s (pss) prescaler s is a 13-bit counter using the system clock ( ) as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by timer a, timer f, sci3, the a/d converter, the lcd controller, and the 10-bit pwm. the divider ratio can be set separately for each on-chip peripheral function. in active (medium-speed) mode the clock input to prescaler s is osc/16, osc/32, osc/64, or osc/128. 2. prescaler w (psw) prescaler w is a 5-bit counter using a 32.768 khz/38.4 khz signal divided by 4 ( w /4) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x1 and x2. prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma). output from prescaler w can be used to drive timer a, in which case timer a functions as a time base for timekeeping.
rev. 4.00, 05/03, page 104 of 562 4.5 note on oscillators oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask rom and ztat? versions, referring to the examples shown in this section. oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the oscillator element manufacturer. design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. (v ss ) p17 x 1 x 2 v ss osc 2 osc 1 test figure 4.11 example of crystal and ceramic oscillator element arrangement figure 4.12 (1) shows an example measuring circuit with the negative resistance suggested by the oscillator manufacturer. note that if the negative resistance of the circuit is less than that suggested by the oscillator manufacturer, it may be difficult to start the main oscillator. if it is determined that oscillation is not occurring because the negative resistance is lower than the level suggested by the oscillator manufacturer, the circuit may be modified as shown in figure 4.12 (2) through (4). which of the modification suggestions to use and the capacitor capacitance should be decided based upon an evaluation of factors such as the negative resistance and the frequency deviation.
rev. 4.00, 05/03, page 105 of 562 (1) negative resistance measuring circuit (2) oscillator circuit modification suggestion 1 (3) oscillator circuit modification suggestion 2 (4) oscillator circuit modification suggestion 3 c3 osc1 osc2 rf c1 c2 negative resistance, addition of r osc1 osc2 rf c1 c2 modification point modification point modification point osc1 osc2 rf c1 c2 osc1 osc2 rf c1 c2 figure 4.12 negative resistance measurement and circuit modification suggestions 4.5.1 definition of oscillation stabilization wait time figure 4.13 shows the oscillation waveform (osc2), system clock ( ), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator. as shown in figure 4.13, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation stabilization time and wait time) is required.
rev. 4.00, 05/03, page 106 of 562 1. oscillation stabilization time (t rc ) the time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. wait time the time required for the cpu and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized. the wait time setting is selected with standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in system control register 1 (syscr1)). oscillation waveform (osc2) system clock ( ) oscillation stabilization time operating mode standby mode, watch mode, or subactive mode wait time oscillation stabilization wait time active (high-speed) mode or active (medium-speed) mode interrupt accepted figure 4.13 oscillation stabilization wait time when standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted. therefore, when an oscillator element is connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time from the point at which this oscillation waveform starts to change until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizesthat is, the oscillation stabilization timeis required.
rev. 4.00, 05/03, page 107 of 562 the oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time t rc " in the ac characteristics. meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order for the cpu and peripheral functions to operate normally. thus, the time required from interrupt generation until operation of the cpu and peripheral functions is the sum of the above described oscillation stabilization time and wait time. this total time is called the oscillation stabilization wait time, and is expressed by equation (1) below. oscillation stabilization wait time = oscillation stabilization time + wait time = t rc + (8 to 16,384 states) ................. (1) therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation stabilization wait time. in particular, since the oscillation stabilization time is affected by installation circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the oscillator element manufacturer. 4.5.2 notes on use of crystal oscillator element (excluding ceramic oscillator element) when a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. depending on the individual crystal oscillator element characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. in this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. if erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in system control register 1 (syscr1)) to give a longer wait time. for example, if erroneous operation occurs with a wait time setting of 16 states, check the operation with a wait time setting of 1,024 states or more. if the same kind of erroneous operation occurs after a reset as after a state transition, hold the res pin low for a longer period.
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rev. 4.00, 05/03, page 109 of 562 section 5 power-down modes 5.1 overview the lsi has nine modes of operation after a reset. these include eight power-down modes, in which power dissipation is significantly reduced. table 5.1 gives a summary of the nine operating modes. table 5.1 operating modes operating mode description active (high-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in high-speed operation active (medium-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock in low-speed operation subactive mode the cpu is operable on the subclock in low-speed operation sleep (high-speed) mode the cpu halts. on-chip peripheral functions are operable on the system clock sleep (medium-speed) mode the cpu halts. on-chip peripheral functions operate at a frequency of 1/128, 1/64, 1/32, or 1/16 of the system clock frequency subsleep mode the cpu halts. the time-base function of timer a, timer c, timer f, timer g, sci3, aec, and lcd controller/driver are operable on the subclock watch mode the cpu halts. the time-base function of timer a, timer f, aec and lcd controller/driver are operable on the subclock standby mode the cpu and all on-chip peripheral functions halt module standby mode individual on-chip peripheral functions specified by software enter standby mode and halt of these nine operating modes, all but the active (high-speed) mode are power-down modes. in this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode.
rev. 4.00, 05/03, page 110 of 562 figure 5.1 shows the transitions among these operation modes. table 5.2 indicates the internal states in each mode. program halt state sleep instruction * e sleep instruction * c sleep instruction * h sleep instruction * i sleep instruction * g sleep instruction * f program execution state sleep instruction * a program halt state sleep instruction * i power-down modes a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that interrupt handling is performed after the interrupt is accepted. details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 to 5.8. notes: 1. 2. mode transition conditions (1) * a * b * c * d * e * f * g * h * i * j lson mson ssby dton 0 0 1 0 * 0 0 0 1 0 0 1 * * * 0 1 1 * 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 * : dont care mode transition conditions (2) * 1 interrupt sources timer a, timer f, timer g interrupt, irq0 interrupt, wkp7 to wkp0 interrupts timer a, timer c, timer f, timer g, sci3 interrupt, irq4, irq3, irq1 and irq0 interrupts, irqaec, wkp7 to wkp0 interrupts, aec all interrupts irq1 or irq0 interrupt, wkp7 to wkp0 interrupts * 2 * 3 * 4 * 3 * 3 * 2 * 1 * 4 * 4 * 1 standby mode watch mode subactive mode active (medium-speed) mode active (high-speed) mode sleep (high-speed) mode sleep (medium-speed) mode subsleep mode sleep instruction * a sleep instruction * e sleep instruction * d sleep instruction * b sleep instruction * j * 1 sleep instruction * e sleep instruction * b tma3 * * 1 0 1 * * 1 1 1 sleep instruction * d reset state figure 5.1 mode transition diagram
rev. 4.00, 05/03, page 111 of 562 table 5.2 internal state in each operating mode active mode sleep mode function high- speed medium- speed high- speed medium- speed watch mode subactive mode subsleep mode standby mode system clock oscillator functions functions functions functions halted halted halted halted subclock oscillator functions functions functions functions functions functions functions functions instructions functions functions halted halted halted functions halted halted cpu operations ram retained retained retained retained retained registers i/o ports retained * 1 irq 0 functions functions functions functions functions functions functions functions external interrupts irq 1 retained * 6 irqaec retained * 6 irq 3 irq 4 wkp 0 functions functions functions functions functions functions functions functions wkp 1 wkp 2 wkp 3 wkp 4 wkp 5 wkp 6 wkp 7 timer a functions functions functions functions functions * 5 functions * 5 functions * 5 retained peripheral functions asynchronous event counter functions * 8 functions functions functions * 8 timer c retained functions/ retained * 2 functions/ retained * 2 retained wdtfunctions/ retained * 7 retained timer f timer g functions/ retained * 9 functions/ retained * 9 functions/ retained * 9 retained sci3 reset functions/ retained * 3 functions/ retained * 3 reset pwm retained retained retained retained a/d converter retained retained retained retained lcd functions/ retained * 4 functions/ retained * 4 functions/ retained * 4 retained notes: * 1 register contents are retained, but output is high-impedance state. port 5 of the hd64f38024 retains the previous pin state. * 2 functions if an external clock or the w /4 internal clock is selected; otherwise halted and retained. * 3functions if w /2 is selected as the internal clock; otherwise halted and retained. * 4functions if w , w /2 or w /4 is selected as the operating clock; otherwise halted and retained. * 5 functions if the timekeeping time-base function is selected. * 6 external interrupt requests are ignored. interrupt request register contents are not altered. * 7functions if w /32 is selected as the internal clock; otherwise halted and retained. * 8 incrementing is possible, but interrupt generation is not. * 9functions if w /4 is selected as the internal clock; otherwise halted and retained.
rev. 4.00, 05/03, page 112 of 562 5.1.1 system control registers the operation mode is selected using the system control registers described in table 5.3. table 5.3 system control registers name abbreviation r/w initial value address system control register 1 syscr1 r/w h'07 h'fff0 system control register 2 syscr2 r/w h'f0 h'fff1 1. system control register 1 (syscr1) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 1 1 ma1 1 r/w syscr1 is an 8-bit read/write register for control of the power-down modes. upon reset, syscr1 is initialized to h'07. bit 7: software standby (ssby) this bit designates transition to standby mode or watch mode. bit 7 ssby description 0 ? when a sleep instruction is executed in active mode, (initial value) a transition is made to sleep mode ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode 1 ? when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode
rev. 4.00, 05/03, page 113 of 562 bits 6 to 4: standby timer select 2 to 0 (sts2 to sts0) these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. the designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 000wait time = 8, 192 states (initial value) 001wait time = 16,384 states 010wait time = 1, 024 states 011wait time = 2, 048 states 100wait time = 4, 096 states 101wait time = 2 states(external clock mode) 110wait time = 8 states 111wait time = 16 states note: in the case that external clock is input, set up the standby timer select selection to external clock mode before mode transition. also, do not set up to external clock mode, in the case that it does not use external clock. bit 3: low speed on flag (lson) this bit chooses the system clock ( ) or subclock ( sub ) as the cpu operating clock when watch mode is cleared. the resulting operation mode depends on the combination of other control bits and interrupt input. bit 3 lson description 0 the cpu operates on the system clock ( ) (initial value) 1 the cpu operates on the subclock ( sub ) bit 2: reserved bit bit 2 is reserved: it is always read as 1 and cannot be modified.
rev. 4.00, 05/03, page 114 of 562 bits 1 and 0: active (medium-speed) mode clock select (ma1, ma0) bits 1 and 0 choose osc /128, osc /64, osc /32, or osc /16 as the operating clock in active (medium- speed) mode and sleep (medium-speed) mode. ma1 and ma0 should be written in active (high- speed) mode or subactive mode. bit 1 ma1 bit 0 ma0 description 00 osc /16 01 osc /32 10 osc /64 11 osc /128 (initial value) 2. system control register 2 (syscr2) bit initial value read/write 7 1 6 1 5 1 4 nesel 1 r/w 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w syscr2 is an 8-bit read/write register for power-down mode control. bits 7 to 5: reserved bits these bits are reserved; they are always read as 1, and cannot be modified. bit 4: noise elimination sampling frequency select (nesel) this bit selects the frequency at which the watch clock signal ( w ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( osc ) generated by the system clock pulse generator. when osc = 2 to 16 mhz, clear nesel to 0. bit 4 nesel description 0 sampling rate is osc /16 1 sampling rate is osc /4 (initial value)
rev. 4.00, 05/03, page 115 of 562 bit 3: direct transfer on flag (dton) this bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a sleep instruction is executed. the mode to which the transition is made after the sleep instruction is executed depends on a combination of other control bits. bit 3 dton description 0 ? when a sleep instruction is executed in active mode, (initial value) a transition is made to standby mode, watch mode, or sleep mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 ? when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 bit 2: medium speed on flag (mson) after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. bit 2 mson description 0 operation in active (high-speed) mode (initial value) 1 operation in active (medium-speed) mode
rev. 4.00, 05/03, page 116 of 562 bits 1 and 0: subactive mode clock select (sa1, sa0) these bits select the cpu clock rate ( w /2, w /4, or w /8) in subactive mode. sa1 and sa0 cannot be modified in subactive mode. bit 1 sa1 bit 0 sa0 description 00 w /8 (initial value) 01 w /4 1 * w /2 * : dont care
rev. 4.00, 05/03, page 117 of 562 5.2 sleep mode 5.2.1 transition to sleep mode 1. transition to sleep (high-speed) mode the system goes from active mode to sleep (high-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson and dton bits in syscr2 are cleared to 0. in sleep mode cpu operation is halted but the on-chip peripheral functions. cpu register contents are retained. 2. transition to sleep (medium-speed) mode the system goes from active mode to sleep (medium-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is cleared to 0. in sleep (medium-speed) mode, as in sleep (high-speed) mode, cpu operation is halted but the on-chip peripheral functions are operational. the clock frequency in sleep (medium-speed) mode is determined by the ma1 and ma0 bits in syscr1. cpu register contents are retained. furthermore, it sometimes acts with half state early timing at the time of transition to sleep (medium-speed) mode. 5.2.2 clearing sleep mode sleep mode is cleared by any interrupt (timer a, timer c, timer f, timer g, asynchronous event counter, irqaec, irq 4 , irq 3 , irq 1 , irq 0 , wkp 7 to wkp 0 , sci3, a/d converter), or by input at the res pin. ? clearing by interrupt when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. a transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. to synchronize the interrupt request signal with the system clock, up to 2/ (s) delay may occur after the interrupt request signal occurrence, before the interrupt exception handling start. ? clearing by res input when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared.
rev. 4.00, 05/03, page 118 of 562 5.2.3 clock frequency in sleep (medium-speed) mode operation in sleep (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1. 5.3 standby mode 5.3.1 transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and bit tma3 in tma is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of cpu registers, on-chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be further retained down to a minimum ram data retention voltage. the i/o ports go to the high-impedance state. port 5 of the hd64f38024 retains the previous pin state. 5.3.2 clearing standby mode standby mode is cleared by an interrupt (irq 1 or irq 0 ), wkp 7 to wkp 0 or by input at the res pin. ? clearing by interrupt when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. operation resumes in active (high-speed) mode if mson = 0 in syscr2, or active (medium-speed) mode if mson = 1. standby mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input when the res pin goes low, the system clock pulse generator starts. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes.
rev. 4.00, 05/03, page 119 of 562 5.3.3 oscillator stabilization time after standby mode is cleared bits sts2 to sts0 in syscr1 should be set as follows. ? when a oscillator is used the table below gives settings for various operating frequencies. set bits sts2 to sts0 for a wait time at least as long as the oscillation stabilization time. table 5.4 clock frequency and stabilization time (times are in ms) sts2 sts1 sts0 wait time 5 mhz 2 mhz 0008, 192 states 1.638 4.1 0 0 1 16,384 states 3.277 8.2 0101, 024 states 0.205 0.512 0112, 048 states 0.410 1.024 1004, 096 states 0.819 2.048 1012 states (use prohibited) 0.0004 0.001 1108 states 0.002 0.004 1 1 1 16 states 0.003 0.008 ? when an external clock is used sts2 = 1, sts1 = 0, and sts0 = 1 should be set. other values possible use, but cpu sometimes will start operation before wait time completion.
rev. 4.00, 05/03, page 120 of 562 5.3.4 standby mode transition and pin states when a sleep instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, and bit tma3 is cleared to 0 in tma, a transition is made to standby mode. at the same time, pins go to the high- impedance state (except pins for which the pull-up mos is designated as on). port 5 of the hd64f38024 retains the previous pin state. figure 5.2 shows the timing in this case. sleep instruction fetch internal data bus fetch of next instruction port output pins high-impedance active (high-speed) mode or active (medium-speed) mode standby mode sleep instruction execution internal processing figure 5.2 standby mode transition and pin states
rev. 4.00, 05/03, page 121 of 562 5.3.5 notes on external input signal changes before/after standby mode 1. when external input signal changes before/after standby mode or watch mode when an external input signal such as irq , wkp , or irqaec is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock sub (referred to together in this section as the internal clock). as the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. ensure that external input signals conform to the conditions stated in 3, recommended timing of external input signals, below 2. when external input signals cannot be captured because internal clock stops the case of falling edge capture is illustrated in figure 5.3. as shown in the case marked "capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 t cyc or 2 t subcyc . 3. recommended timing of external input signals to ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 t cyc or 2 t subcyc are necessary before a transition is made to standby mode or watch mode, as shown in "capture possible: case 1." external input signal capture is also possible with the timing shown in "capture possible: case 2" and "capture possible: case 3," in which a 2 t cyc or 2 t subcyc level width is secured.
rev. 4.00, 05/03, page 122 of 562 t cyc t subcyc operating mode or sub capture possible: case 1 capture possible: case 2 capture possible: case 3 capture not possible interrupt by different signal external input signal active (high-speed, medium-speed) mode or subactive mode active (high-speed, medium-speed) mode or subactive mode standby mode or watch mode wait for oscillation to settle t cyc t subcyc t cyc t subcyc t cyc t subcyc figure 5.3 external input signal capture when signal changes before/after standby mode or watch mode 4. input pins to which these notes apply: irq 4 , irq 3 , irq 1 , irq 0 , wkp 7 to wkp 0 , irqaec, tmic, tmif, tmig, adtrg .
rev. 4.00, 05/03, page 123 of 562 5.4 watch mode 5.4.1 transition to watch mode the system goes from active or subactive mode to watch mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1. in watch mode, operation of on-chip peripheral modules is halted except for timer a, timer f, timer g, aec and the lcd controller/driver (for which operation or halting can be set) is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules, are retained. i/o ports keep the same states as before the transition. 5.4.2 clearing watch mode watch mode is cleared by an interrupt (timer a, timer f, timer g, irq0, or wkp7 to wkp0) or by input at the res pin. ? clearing by interrupt when watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of lson in syscr1 and mson in syscr2. if both lson and mson are cleared to 0, transition is to active (high-speed) mode; if lson = 0 and mson = 1, transition is to active (medium-speed) mode; if lson = 1, transition is to subactive mode. when the transition is to active mode, after the time set in syscr1 bits sts2 to sts0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. watch mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. ? clearing by res input clearing by res pin is the same as for standby mode; see 2. clearing by res pin in section 5.3.2, clearing standby mode. 5.4.3 oscillator stabilizationtime after watch mode is cleared the wait time is the same as for standby mode; see section 5.3.3, oscillator stabilization time after standby mode is cleared. 5.4.4 notes on external input signal changes before/after watch mode see section 5.3.5, notes on external input signal changes before/after standby mode.
rev. 4.00, 05/03, page 124 of 562 5.5 subsleep mode 5.5.1 transition to subsleep mode the system goes from subactive mode to subsleep mode when a sleep instruction is executed while the ssby bit in syscr1 is cleared to 0, lson bit in syscr1 is set to 1, and tma3 bit in tma is set to 1. in subsleep mode, operation of on-chip peripheral modules other than the a/d converter and pwm is in active state. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. 5.5.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a, timer c, timer f, timer g, asynchronous event counter, sci3, irqaec, irq 4 , irq 3 , irq 1 , irq 0 , wkp 7 to wkp 0 ) or by a low input at the res pin. ? clearing by interrupt when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. to synchronize the interrupt request signal with the subclock, up to 2/ sub (s) delay may occur after the interrupt request signal occurrence, before the interrupt exception handling start. ? clearing by res input clearing by res pin is the same as for standby mode; see clearing by res pin in section 5.3.2, clearing standby mode.
rev. 4.00, 05/03, page 125 of 562 5.6 subactive mode 5.6.1 transition to subactive mode subactive mode is entered from watch mode if a timer a, timer f, timer g, irq 0 , or wkp 7 to wkp 0 interrupt is requested while the lson bit in syscr1 is set to 1. from subsleep mode, subactive mode is entered if a timer a, timer c, timer f, timer g, asynchronous event counter, sci3, irqaec, irq 4 , irq 3 , irq 1 , irq 0 , or wkp 7 to wkp 0 interrupt is requested. a transition to subactive mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 clearing subactive mode subactive mode is cleared by a sleep instruction or by a low input at the res pin. ? clearing by sleep instruction if a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and tma3 bit in tma is set to 1, subactive mode is cleared and watch mode is entered. if a sleep instruction is executed while ssby = 0 and lson = 1 in syscr1 and tma3 = 1 in tma, subsleep mode is entered. direct transfer to active mode is also possible; see section 5.8, direct transfer, below. ? clearing by res pin clearing by res pin is the same as for standby mode; see clearing by res pin in section 5.3.2, clearing standby mode. 5.6.3 operating frequency in subactive mode the operating frequency in subactive mode is set in bits sa1 and sa0 in syscr2. the choices are w /2, w /4, and w /8.
rev. 4.00, 05/03, page 126 of 562 5.7 active (medium-speed) mode 5.7.1 transition to active (medium-speed) mode if the mson bit in syscr2 is set to 1 while the lson bit in syscr1 is cleared to 0, a transition to active (medium-speed) mode results from irq 0 , irq 1 or wkp 7 to wkp 0 interrupts in standby mode, timer a, timer f, timer g, irq 0 , or wkp 7 to wkp 0 interrupts in watch mode, or any interrupt in sleep mode. a transition to active (medium-speed) mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. furthermore, it sometimes acts with half state early timing at the time of transition to active (medium-speed) mode. 5.7.2 clearing active (medium-speed) mode active (medium-speed) mode is cleared by a sleep instruction. ? clearing by sleep instruction a transition to standby mode takes place if the sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and the tma3 bit in tma is cleared to 0. the system goes to watch mode if the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1 when a sleep instruction is executed. when both ssby and lson are cleared to 0 in syscr1 and a sleep instruction is executed, sleep mode is entered. direct transfer to active (high-speed) mode or to subactive mode is also possible. see section 5.8, direct transfer, below for details. ? clearing by res pin when the res pin is driven low, a transition is made to the reset state and active (medium- speed) mode is cleared. 5.7.3 operating frequency in active (medium-speed) mode operation in active (medium-speed) mode is clocked at the frequency designated by the ma1 and ma0 bits in syscr1.
rev. 4.00, 05/03, page 127 of 562 5.8 direct transfer 5.8.1 overview of direct transfer the cpu can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. a direct transfer is a transition among these three modes without the stopping of program execution. a direct transfer can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. after the mode transition, direct transfer interrupt exception handling starts. if the direct transfer interrupt is disabled in interrupt enable register 2 (ienr2), a transition is made instead to sleep mode or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. ? direct transfer from active (high-speed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. ? direct transfer from active (medium-speed) mode to active (high-speed) mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. ? direct transfer from active (high-speed) mode to subactive mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. ? direct transfer from active (medium-speed) mode to subactive mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode.
rev. 4.00, 05/03, page 128 of 562 ? direct transfer from subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 5.8.2 direct transition times 1. time for direct transition from active (high-speed) mode to active (medium-speed) mode a direct transition from active (high-speed) mode to active (medium-speed) mode is performed by executing a sleep instruction in active (high-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bits mson and dton are both set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (1) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (1) example: direct transition time = (2 + 1) 2tosc + 14 16tosc = 230tosc (when /8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock ( ) cycle time
rev. 4.00, 05/03, page 129 of 562 2. time for direct transition from active (medium-speed) mode to active (high-speed) mode a direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a sleep instruction in active (medium-speed) mode while bits ssby and lson are both cleared to 0 in syscr1, and bit mson is cleared to 0 and bit dton is set to 1 in syscr2. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (2) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tcyc before transition) + (number of interrupt exception handling execution states) (tcyc after transition) .................................. (2) example: direct transition time = (2 + 1) 16tosc + 14 2tosc = 76tosc (when /8 is selected as the cpu operating clock) notation: tosc: osc clock cycle time tcyc: system clock ( ) cycle time 3. time for direct transition from subactive mode to active (high-speed) mode a direct transition from subactive mode to active (high-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bit mson is cleared to 0 and bit dton is set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (3) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (3) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 2tosc = 24tw + 16412tosc (when w/8 is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time
rev. 4.00, 05/03, page 130 of 562 4. time for direct transition from subactive mode to active (medium-speed) mode a direct transition from subactive mode to active (medium-speed) mode is performed by executing a sleep instruction in subactive mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, bits mson and dton are both set to 1 in syscr2, and bit tma3 is set to 1 in tma. the time from execution of the sleep instruction to the end of interrupt exception handling (the direct transition time) is given by equation (4) below. direct transition time = { (number of sleep instruction execution states) + (number of internal processing states) } (tsubcyc before transition) + { (wait time set in sts2 to sts0) + (number of interrupt exception handling execution states) } (tcyc after transition) ........................ (4) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 16tosc = 24tw + 131296tosc (when w/8 or /8 is selected as the cpu operating clock, and wait time = 8192 states) notation: tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time 5.8.3 notes on external input signal changes before/after direct transition 1. direct transition from active (high-speed) mode to subactive mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode. 2. direct transition from active (medium-speed) mode to subactive mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode. 3. direct transition from subactive mode to active (high-speed) mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode. 4. direct transition from subactive mode to active (medium-speed) mode since the mode transition is performed via watch mode, see section 5.3.5, notes on external input signal changes before/after standby mode.
rev. 4.00, 05/03, page 131 of 562 5.9 module standby mode 5.9.1 setting module standby mode module standby mode is set for individual peripheral functions. all the on-chip peripheral modules can be placed in module standby mode. when a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. this state is identical to standby mode. module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) 5.9.2 clearing module standby mode module standby mode is cleared for a particular module by setting the corresponding bit to 1 in clock stop register 1 (ckstpr1) or clock stop register 2 (ckstpr2). (see table 5.5.) following a reset, clock stop register 1 (ckstpr1) and clock stop register 2 (ckstpr2) are both initialized to h'ff. table 5.5 setting and clearing module standby mode by clock stop register register name bit name operation ckstpr1 tackstp 1 timer a module standby mode is cleared 0 timer a is set to module standby mode tcckstp 1 timer c module standby mode is cleared 0 timer c is set to module standby mode tfckstp 1 timer f module standby mode is cleared 0 timer f is set to module standby mode tgckstp 1 timer g module standby mode is cleared 0 timer g is set to module standby mode adckstp 1 a/d converter module standby mode is cleared 0 a/d converter is set to module standby mode s32ckstp 1 sci3 module standby mode is cleared 0 sci3 is set to module standby mode
rev. 4.00, 05/03, page 132 of 562 register name bit name operation ckstpr2 ldckstp 1 lcd module standby mode is cleared 0 lcd is set to module standby mode pw1ckstp 1 pwm1 module standby mode is cleared 0 pwm1 is set to module standby mode wdckstp 1 watchdog timer module standby mode is cleared 0 watchdog timer is set to module standby mode aeckstp 1 asynchronous event counter module standby mode is cleared 0 asynchronous event counter is set to module standby mode pw2ckstp 1 pwm2 module standby mode is cleared 0 pwm2 is set to module standby mode note: for details of module operation, see the sections on the individual modules.
rev. 4.00, 05/03, page 133 of 562 section 6 rom 6.1 overview the h8/38024 and h8/38024s have 32 kbytes of on-chip mask rom, the h8/38023 and h8/38023s have 24 kbytes, the h8/38022 and h8/38022s have 16 kbytes, the h8/38021 and h8/38021s have 12 kbytes, and the h8/38020 and h8/38020s have 8 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. the h8/38024 has a ztat version and f-ztat version with 32-kbyte prom and flash memory. 6.1.1 block diagram figure 6.1 shows a block diagram of the on-chip rom. h7ffe h7fff internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h7ffe h0002 h0000 h0000 h0002 h0001 h0003 on-chip rom figure 6.1 rom block diagram (h8/38024)
rev. 4.00, 05/03, page 134 of 562 6.2 h8/38024 prom mode 6.2.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the standard hn27c101 eprom. however, page programming is not supported. table 6.1 shows how to set the chip to prom mode. table 6.1 setting to prom mode pin name setting test high level pb 0 /an 0 low level pb 1 /an 1 pb 2 /an 2 high level 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 32 pins. figure 6.2 shows the pin-to-pin wiring of the socket adapter. figure 6.3 shows a memory map.
rev. 4.00, 05/03, page 135 of 562 hn27c101 (32-pin) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 v cc v ss note: pins not indicated in the figure should be left open. eprom socket fp-80a, tfp-80c fp-80b pin 12 21 22 23 24 25 26 27 28 69 70 63 64 65 66 67 68 29 72 31 32 33 34 35 57 58 36 30 56 52 1 11 75 54 55 59 53 8 6 73 74 14 23 24 25 26 27 28 29 30 71 72 65 66 67 68 69 70 31 74 33 34 35 36 37 59 60 38 32 58 54 3 13 77 56 57 61 55 10 8 75 76 p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p4 0 p4 1 p3 2 p3 3 p3 4 p3 5 p3 6 p3 7 p7 0 p4 3 p7 2 p7 3 p7 4 p7 5 p7 6 p9 3 p9 4 p7 7 p7 1 p9 2 v cc av cc test pb 2 p9 0 p9 1 p9 5 v ss v ss = av ss x 1 pb 0 pb 1 h8/38024 figure 6.2 socket adapter pin correspondence (with hn27c101)
rev. 4.00, 05/03, page 136 of 562 address in mcu mode address in prom mode h0000 h0000 h1ffff h7fff h7fff on-chip prom uninstalled area * the output data is not guaranteed if this address area is read in prom mode. therefore, when programming with a prom programmer, be sure to specify addresses from h0000 to h7fff. if programming is inadvertently performed from h8000 onward, it may not be possible to continue prom programming and verification. when programming, hff should be set as the data in this address area (h8000 to h1ffff). note: * figure 6.3 h8/38024 memory map in prom mode
rev. 4.00, 05/03, page 137 of 562 6.3 h8/38024 programming the write, verify, and other modes are selected as shown in table 6.2 in h8/38024 prom mode. table 6.2 mode selection in prom mode (h8/38024) pins mode ce ce ce ce oe oe oe oe pgm pgm pgm pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write l h l v pp v cc data input address input verify l l h v pp v cc data output address input programming l l l v pp v cc high impedance address input disabled l h h hl l hhh notation l: low level h: high level v pp :v pp level v cc :v cc level the specifications for writing and reading are identical to those for the standard hn27c101 eprom. however, page programming is not supported, and so page programming mode must not be set. a prom programmer that only supports page programming mode cannot be used. when selecting a prom programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. also, be sure to specify addresses from h'0000 to h'7fff. 6.3.1 writing and verifying an efficient, high-speed, high-reliability method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. the basic flow of this high-speed, high-reliability programming method is shown in figure 6.4.
rev. 4.00, 05/03, page 138 of 562 start set write/verify mode v = 6.0 v 0.25 v, v = 12.5 v 0.3 v cc pp address = 0 n = 0 n + 1 n pw verify write time t = 0.2n ms opw last address? set read mode v = 5.0 v 0.25 v, v = v cc pp cc read all addresses? end error n 25 address + 1 address no yes no yes yes no no yes write time t = 0.2 ms 5% figure 6.4 high-speed, high-reliability programming flow chart
rev. 4.00, 05/03, page 139 of 562 tables 6.3 and 6.4 give the electrical characteristics in programming mode. table 6.3 dc characteristics conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min typ max unit test condition input high-level voltage eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm v ih 2.4 v cc + 0.3 v input low- level voltage eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm v il C0.3 0.8 v output high-level voltage eo 7 to eo 0 v oh 2.4 v i oh = C200 a output low-level voltage eo 7 to eo 0 v ol 0.45 v i ol = 0.8 ma input leakage current eo 7 to eo 0 , ea 16 to ea 0 , oe , ce , pgm |i li | 2 av in = 5.25 v/ 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma
rev. 4.00, 05/03, page 140 of 562 table 6.4 ac characteristics conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25c 5c item symbol min typ max unit test condition address setup time t as 2 s figure 6.5 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 5.25 ms ce setup time t ces 2 s v cc setup time t vcs 2 s data output delay time t oe 0 200 ns notes: * 1 input pulse level: 0.45 v to 2.4 v input rise time/fall time 20 ns timing reference levels input: 0.8 v, 2.0 v output: 0.8 v, 2.0 v * 2t df is defined at the point at which the output is floating and the output level cannot be read. * 3t opw is defined by the value given in figure 6.4, high-speed, high-reliability programming flow chart.
rev. 4.00, 05/03, page 141 of 562 figure 6.5 shows a prom write/verify timing diagram. write input data output data verify address data v pp v pp t as t ah t ds t dh t df t oe t oes t pw t opw * t vps t vcs t ces v cc v cc v cc +1 v cc note: * t opw is defined by the value shown in figure 6.4, high-speed, high-reliability programming flowchart. figure 6.5 prom write/verify timing
rev. 4.00, 05/03, page 142 of 562 6.3.2 programming precautions ? use the specified programming voltage and timing. the programming voltage in prom mode (v pp ) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to renesas specifications for the hn27c101 will result in correct v pp of 12.5 v. ? make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure that the chip is properly mounted in the prom programmer. ? avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. ? take care when setting the programming mode, as page programming is not supported. ? when programming with a prom programmer, be sure to specify addresses from h'0000 to h'7fff. if programming is inadvertently performed from h'8000 onward, it may not be possible to continue prom programming and verification. when programming, h'ff should be set as the data in address area h'8000 to h'1ffff.
rev. 4.00, 05/03, page 143 of 562 6.4 reliability of programmed data a highly effective way to improve data retention characteristics is to bake the programmed chips at 150c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 6.6 shows the recommended screening procedure. program chip and verify programmed data bake chip for 24 to 48 hours at 125 c to 150 c with power off read and check program install figure 6.6 recommended screening procedure if a series of programming errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform renesas technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
rev. 4.00, 05/03, page 144 of 562 6.5 flash memory overview 6.5.1 features the features of the 32-kbyte flash memory built into hd64f38024 and hd64f38024r are summarized below. ? programming/erase methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: 1 kbyte 4 blocks, 28 kbytes 1 block. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability ? the hd64f38024r can be reprogrammed up to 1,000 times and the hd64f38024 up to 100 times. ? on-board programming ? on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? programmer mode ? flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment ? for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection ? sets software protection against flash memory programming/erasing. ? power-down mode ? the power supply circuit is partly halted in the subactive mode and can be read in the power-down mode.
rev. 4.00, 05/03, page 145 of 562 6.5.2 block diagram internal address bus module bus internal data bus (16 bits) flmcr1 bus interface/controller operating mode tes pin p95 pin p34 pin notation flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr: erase block register flpwcr: flash memory power control register fenr: flash memory enable register flmcr2 ebr flpwcr fenr flash memory (32 kbytes) figure 6.7 block diagram of flash memory
rev. 4.00, 05/03, page 146 of 562 6.5.3 block configuration figure 6.8 shows the block configuration of 32-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 1 kbyte 4 blocks and 28 kbytes 1 block. erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. h007f h0000 h0001 h0002 h00ff h0080 h0081 h0082 h03ff h0380 h0381 h0382 h047f h0400 h0401 h0402 h04ff h0480 h0481 h0482 h07ff h0780 h0781 h0782 h087f h0800 h0801 h0802 h08ff h0880 h0881 h0882 h0bff h0b80 h0b81 h0b82 h0c7f h0c00 h0c01 h0c02 h0cff h0c80 h0c81 h0c82 h0fff h0f80 h0f81 h0f82 h107f h1000 h1001 h1002 h10ff h1080 h1081 h1082 h7fff h7f80 h7f81 h7f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 28 kbytes erase unit figure 6.8 flash memory block configuration
rev. 4.00, 05/03, page 147 of 562 6.5.4 register configuration table 6.5 lists the register configuration to control the flash memory when the built in flash memory is effective. table 6.5 register configuration register name abbreviation r/w initial value address flash memory control register 1 flmcr1 r/w h'00 h'f020 flash memory control register 2 flmcr2 r h'00 h'f021 flash memory power control register flpwcr r/w h'00 h'f022 erase block register ebr r/w h'00 h'f023 flash memory enable register fenr r/w h'00 h'f02b note: flmcr1, flmcr2, flpwcr, ebr, and fenr are 8 bit registers. only byte access is enabled which are two-state access. these registers are dedicated to the product in which flash memory is included. the product in which prom or rom is included does not have these registers. when the corresponding address is read in these products, the value is undefined. a write is disabled.
rev. 4.00, 05/03, page 148 of 562 6.6 descriptions of registers of the flash memory 6.6.1 flash memory control register 1 (flmcr1) bit 76543210 swe esu psu ev pv e p initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 6.8, flash memory programming/erasing. by setting this register, the flash memory enters program mode, erase mode, program-verify mode, or erase-verify mode. read the data in the state that bits 6 to 0 of this register are cleared when using flash memory as normal built-in rom. bit 7: reserved bit this bit is always read as 0 and cannot be modified. bit 6: software write enable (swe) this bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to 0 and the ebr register are to be set). bit 6 swe description 0 programming/erasing is disabled. other flmcr1 register bits and all ebr bits cannot be set. (initial value) 1 flash memory programming/erasing is enabled. bit 5: erase setup (esu) this bit is to prepare for changing to erase mode. set this bit to 1 before setting the e bit to 1 in flmcr1 (do not set swe, psu, ev, pv, e, and p bits at the same time). bit 5 esudescription 0 the erase setup state is cancelled (initial value) 1 the flash memory changes to the erase setup state. set this bit to 1 before setting the e bit to 1 in flmcr1.
rev. 4.00, 05/03, page 149 of 562 bit 4: program setup (psu) this bit is to prepare for changing to program mode. set this bit to 1 before setting the p bit to 1 in flmcr1 (do not set swe, esu, ev, pv, e, and p bits at the same time). bit 4 psudescription 0 the program setup state is cancelled (initial value) 1 the flash memory changes to the program setup state. set this bit to 1 before setting the p bit to 1 in flmcr1. bit 3: erase-verify (ev) this bit is to set changing to or cancelling erase-verify mode (do not set swe, esu, psu, pv, e, and p bits at the same time). bit 3 ev description 0 erase-verify mode is cancelled (initial value) 1 the flash memory changes to erase-verify mode bit 2: program-verify (pv) this bit is to set changing to or cancelling program-verify mode (do not set swe, esu, psu, ev, e, and p bits at the same time). bit 2 pv description 0 program-verify mode is cancelled (initial value) 1 the flash memory changes to program-verify mode bit 1: erase (e) this bit is to set changing to or cancelling erase mode (do not set swe, esu, psu, ev, pv, and p bits at the same time). bit 1 e description 0 erase mode is cancelled (initial value) 1 when this bit is set to 1, while the swe = 1 and esu = 1, the flash memory changes to erase mode.
rev. 4.00, 05/03, page 150 of 562 bit 0: program (p) this bit is to set changing to or cancelling program mode (do not set swe, esu, psu, ev, pv, and e bits at the same time). bit 0 p description 0 program mode is cancelled (initial value) 1 when this bit is set to 1, while the swe = 1 and psu = 1, the flash memory changes to program mode. 6.6.2 flash memory control register 2 (flmcr2) bit 76543210 fler initial value00000000 read/write r flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit 7: flash memory error (fler) this bit is set when the flash memory detects an error and goes to the error-protection state during programming or erasing to the flash memory. see section 6.9.3, error protection, for details. bit 7 fler description 0 the flash memory operates normally. (initial value) 1 indicates that an error has occurred during an operation on flash memory (programming or erasing). bits 6 to 0: reserved bits these bits are always read as 0 and cannot be modified.
rev. 4.00, 05/03, page 151 of 562 6.6.3 erase block register (ebr) bit 76543210 eb4 eb3 eb2 eb1 eb0 initial value00000000 read/write r/w r/w r/w r/w r/w ebr specifies the flash memory erase area block. ebr is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr to be automatically cleared to 0. when each bit is set to 1 in ebr, the corresponding block can be erased. other blocks change to the erase-protection state. see table 6.6 for the method of dividing blocks of the flash memory. when the whole bits are to be erased, erase them in turn in unit of a block. table 6.6 division of blocks to be erased ebr bit name block (size) address 0 eb0 eb0 (1 kbyte) h'0000 to h'03ff 1 eb1 eb1 (1 kbyte) h'0400 to h'07ff 2 eb2 eb2 (1 kbyte) h'0800 to h'0bff 3 eb3 eb3 (1 kbyte) h'0c00 to h'0fff 4 eb4 eb4 (28 kbytes) h'1000 to h'7fff 6.6.4 flash memory power control register (flpwcr) bit 76543210 pdwnd initial value00000000 read/write r/w flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. the power supply circuit can be read in the subactive mode, although it is partly halted in the power-down mode. bit 7: power-down disable (pdwnd) this bit selects the power-down mode of the flash memory when a transition to the subactive mode is made.
rev. 4.00, 05/03, page 152 of 562 bit 7 pdwnd description 0 when this bit is 0 and a transition is made to the subactive mode, the flash memory enters the power-down mode. (initial value) 1 when this bit is 1, the flash memory remains in the normal mode even after a transition is made to the subactive mode. bits 6 to 0: reserved bits these bits are always read as 0 and cannot be modified. 6.6.5 flash memory enable register (fenr) bit 76543210 flshe initial value00000000 read/write r/w fenr controls cpu access to the flash memory control registers, flmcr1, flmcr2, ebr, and flpwcr. bit 7: flash memory control register enable (flshe) this bit controls access to the flash memory control registers. bit 7 flshe description 0 flash memory control registers cannot be accessed (initial value) 1 flash memory control registers can be accessed bits 6 to 0: reserved bits these bits are always read as 0 and cannot be modified.
rev. 4.00, 05/03, page 153 of 562 6.7 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, the series of hd64f38024 and hd64f38024r changes to a mode depending on the test pin settings, p95 pin settings, and input level of each port, as shown in table 6.7. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 6.7 setting programming modes test p95 p34 pb0 pb1 pb2 lsi state after reset end 0 1 xxxxuser mode 0 0 1 xxxboot mode 1xx000programmer mode x: dont care
rev. 4.00, 05/03, page 154 of 562 6.7.1 boot mode table 6.8 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 6.8, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. the inversion function of txd and rxd pins by the spcr register is set to not to be inverted, so do not put the circuit for inverting a value between the host and this lsi. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 6.9. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'f780 to h'feef is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high (pcr42 = 1, p42 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the test pin and p95 pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and p95 pin input levels in boot mode.
rev. 4.00, 05/03, page 155 of 562 table 6.8 boot mode operation item host operation lsi operation branches to boot program at reset-start. processing contents processing contents bit rate adjustment flash memory erase continuously transmits data h00 at specified bit rate. ? measures low-level period of receive data h00. ? calculates bit rate and sets it in brr of sci3. ? transmits data h00 to the host to indicate that the adjustment has ended. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data haa to host. (if erase could not be done, transmits data hff to host and aborts operation.) transmits data h55 when data h00 is received and no error occurs. transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program transfer of programming control program execution of programming control program transfer of programming control program (repeated for n times) echobacks the 2-byte received data to host. transmits 1-byte data haa to host. branches to programming control program transferred to on-chip ram and starts execution. echobacks received data to host and also transfers it to ram. table 6.9 oscillating frequencies (f osc ) for which automatic adjustment of lsi bit rate is possible host bit rate oscillating frequencie s (f osc ) range of lsi 4,800 bps 8 to 10 mhz 2,400 bps 4 to 10 mhz 1,200 bps 2 to 10 mhz
rev. 4.00, 05/03, page 156 of 562 6.7.2 programming/erasing in user program mode the term user mode refers to the status when a user program is being executed. on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 6.9 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 6.8, flash memory programming/erasing. yes no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 6.9 programming/erasing flowchart example in user program mode 6.8 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in
rev. 4.00, 05/03, page 157 of 562 accordance with the descriptions in section 6.8.1, program/program-verify and section 6.8.2, erase/erase-verify, respectively. 6.8.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.10 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 6.10, and additional programming data computation according to table 6.11. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. do not use rts instruction from data transfer to setting p bit to 1. 5. the time during which the p bit is set to 1 is the programming time. figure 6.12 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 1 bit is b'0. verify data can be read in word size from the address to which a dummy write was performed. do not use rts instruction from dummy write to verify data read. 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
rev. 4.00, 05/03, page 158 of 562 start end of programming set swe bit in flmcr1 write pulse application subroutine wait 1 s apply write pulse end sub set psu bit in flmcr1 wdt enable disable wdt wait 50 s set p bit in flmcr1 wait (wait time = programming time) clear p bit in flmcr1 wait 5 s clear psu bit in flmcr1 wait 5 s n = 1 m = 0 no no no yes yes yes yes wait 4 s wait 2 s wait 2 s apply write pulse set pv bit in flmcr1 hff dummy write to verify address read verify data reprogram data computation clear pv bit in flmcr1 clear swe bit in flmcr1 increment address programming failure clear swe bit in flmcr1 wait 100 s no yes no yes no wait 100 s n 1000 ? write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area apply write pulse sub-routine-call successively write 128-byte data from additional-programming data area in ram to flash memory set block start address as verify address n n + 1 m = 1 m = 0 ? n 6? 128-byte data verification completed? n 6 ? additional-programming data computation verify data = write data? figure 6.10 program/program-verify flowch art
rev. 4.00, 05/03, page 159 of 562 table 6.10 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 101 1 1 1 remains in erased state table 6.11 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 6.12 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 note: time shown in s.
rev. 4.00, 05/03, page 160 of 562 6.8.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 1 bit is b'0. verify data can be read in word size from the address to which a dummy write was performed. do not use rts instruction from dummy write to verify data read. 6. if the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 6.8.3 interrupt handling when programming/erasing flash memory all interrupts, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
rev. 4.00, 05/03, page 161 of 562 erase start set ebr enable wdt wait 1 s wait 100 s swe bit 1 n 1 esu bit 1 e bit 1 wait 10 ms e bit 0 wait 10 s esu bit 0 wait 10 s disable wdt read verify data increment address verify data = all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address wait 20 s wait 2 s ev bit 1 wait 100 s end of erasing swe bit 0 wait 4 s ev bit 0 n 100 ? wait 100 s erase failure swe bit 0 wait 4 s ev bit 0 n n + 1 yes no yes yes yes no no no figure 6.11 erase/erase-verify flowchart
rev. 4.00, 05/03, page 162 of 562 6.9 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register (ebr) are initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. 6.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register (ebr), erase protection can be set for individual blocks. when ebr is set to h'00, erase protection is set for all blocks. 6.9.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling excluding a reset during programming/erasing ? when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, and ebr settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset.
rev. 4.00, 05/03, page 163 of 562 6.10 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. use a prom programmer that supports the mcu device type with the on-chip renesas technology 64-kbyte flash memory (f-ztat64v3). a 10- mhz input clock is required. for the conditions for transition to programmer mode, see table 6.7. 6.10.1 socket adapter the socket adapter converts the pin allocation of the hd64f38024 and hd64f38024r to that of the discrete flash memory hn28f101. the address of the on-chip flash memory is h'0000 to h'7fff. figure 6.12 shows the socket-adapter-pin correspondence diagram. 6.10.2 programmer mode commands the following commands are supported in programmer mode. ? memory read mode ? auto-program mode ? auto-erase mode ? status read mode status polling is used for auto-programming, auto-erasing, and status read modes. in status read mode, detailed internal information is output after the execution of auto-programming or auto- erasing. table 6.13 shows the sequence of each command. in auto-programming mode, 129 cycles are required since 128 bytes are written at the same time. in memory read mode, the number of cycles depends on the number of address write cycles (n). table 6.13 command sequence in programmer mode 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read 1 + n write x h'00 read ra dout auto-program 129 write x h'40 write wa din auto-erase 2 write x h'20 write x h'20 status read 2 write x h'71 write x h'71 n: the number of address write cycles
rev. 4.00, 05/03, page 164 of 562 hd64f38024, hd64f38024r fp-80a tfp-80c fp-80b socket adapter (conversion to 32-pin arrangement) pin no. pin name 32 38 58 23 24 25 26 27 28 29 30 71 72 65 66 67 68 69 70 31 73 33 34 35 36 37 74 54 3 8 13 53 54 60 61 10 55 75 76 77 12, 11 14 p71 p77 p92 p60 p61 p62 p63 p64 p65 p66 p67 p40 p41 p32 p33 p34 p35 p36 p37 p70 p42 p72 p73 p74 p75 p76 p43 vcc avcc x1 test v1 vcc p94 p95 vss vss pb0 pb1 pb2 osc1, osc2 (open) hn28f101 (32 pins) pin no. pin name 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 fwe a9 a16 a15 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a10 a11 a12 a13 a14 vcc vss 30 36 56 21 22 23 24 25 26 27 28 69 70 63 64 65 66 67 68 29 71 31 32 33 34 35 72 52 1 6 11 51 52 58 59 8 53 73 74 75 10, 9 12 power-on reset circuit oscillator circuit other than the above legend fwe: flash-write enable i/o7 to i/o0: data input/output a16 to a0: address input : chip enable : output enable : write enable note: the oscillation frequency of the oscillator circuit should be 10 mhz. figure 6.12 socket adapter pin correspondence diagram
rev. 4.00, 05/03, page 165 of 562 6.10.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. once memory read mode has been entered, consecutive reads can be performed. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. after powering on, memory read mode is entered. 4. tables 6.14 to 6.16 show the ac characteristics. table 6.14 ac characteristics in transition to memory read mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s figure 6.13 ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30ns we fall time t f 30ns a15 a0 i/o7 i/o0 note: data is latched on the rising edge of . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 6.13 timing waveforms for memory read after memory write
rev. 4.00, 05/03, page 166 of 562 table 6.15 ac characteristics in transition from memory read mode to another mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s figure 6.14 ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30ns we fall time t f 30ns a15 a0 i/o7 i/o0 note: do not enable and at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 6.14 timing waveforms in transition from memory read mode to another mode
rev. 4.00, 05/03, page 167 of 562 table 6.16 ac characteristics in memory read mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes access time t acc 20 s figure 6.15 ce output delay time t ce 150 ns figure 6.16 oe output delay time t oe 150 ns output disable delay time t df 100 ns data output hold time t oh 5ns a15 a0 i/o7 i/o0 t acc t acc t oh t oh address stable address stable figure 6.15 ce ce ce ce and oe oe oe oe enable state read timing waveforms a15 a0 i/o7 i/o0 t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 6.16 ce ce ce ce and oe oe oe oe clock system read timing waveforms
rev. 4.00, 05/03, page 168 of 562 6.10.4 auto-program mode 1. when reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. perform auto-programming once only on the same address block. it is not possible to program an address block that has already been programmed. 3. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 4. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 5. memory address transfer is performed in the second cycle (figure 6.17). do not perform transfer after the third cycle. 6. do not perform a command write during a programming operation. 7. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 8. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). 9. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 10. table 6.17 shows the ac characteristics.
rev. 4.00, 05/03, page 169 of 562 table 6.17 ac characteristics in auto-program mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s figure 6.17 ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t wsts 1ms status polling access time t spa 150 ns address setup time t as 0ns address hold time t ah 60 ns memory write time t write 1 3000 ms we rise time t r 30ns we fall time t f 30ns a15 a0 i/o7 i/o6 i/o5 i/o0 t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc address stable h40 h00 data transfer 1 to 128 bytes write operation end decision signal write normal end decision signal figure 6.17 auto-program mode timing waveforms
rev. 4.00, 05/03, page 170 of 562 6.10.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 5. table 6.18 shows the ac characteristics. table 6.18 ac characteristics in auto-erase mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s figure 6.18 ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t ests 1ms status polling access time t spa 150 ns memory erase time t erase 100 40000 ms we rise time t r 30ns we fall time t f 30ns
rev. 4.00, 05/03, page 171 of 562 a15 a0 i/o7 i/o6 i/o5 i/o0 t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc h20 h20 h00 ! *$!$!$ !( *$!$!$ figure 6.18 auto-erase mode timing waveforms 6.10.6 status read mode 1. status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. 3. table 6.19 shows the ac characteristics and 6.20 shows the return codes. table 6.19 ac characteristics in status read mode conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c item symbol min max unit notes read time after command write t nxtc 20 s figure 6.19 ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns oe output delay time t oe 150 ns disable delay time t df 100 ns ce output delay time t ce 150 ns we rise time t r 30ns we fall time t f 30ns
rev. 4.00, 05/03, page 172 of 562 a15 a0 i/o7 /o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h71 & 27
)
) $ figure 6.19 status read mode timing waveforms table 6.20 status read mode return codes pin name initial value indications i/o7 0 1: abnormal end 0: normal end i/o6 0 1: command error 0: otherwise i/o5 0 1: programming error 0: otherwise i/o4 0 1: erasing error 0: otherwise i/o3 0 ? i/o2 0 ? i/o1 0 1: over counting of writing or erasing 0: otherwise i/o0 0 1: effective address error 0: otherwise
rev. 4.00, 05/03, page 173 of 562 6.10.7 status polling 1. the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 6.21 status polling output truth table i/o7 i/o6 i/o0 to 5 status 0 0 0 during internal operation 1 0 0 abnormal end 1 1 0 normal end 010 6.10.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 6.22 stipulated transition times to command wait state item symbol min max unit notes oscillation stabilization time(crystal oscillator) t osc1 10 ms figure 6.20 oscillation stabilization time(ceramic oscillator) t osc1 5ms programmer mode setup time t bmv 10 ms vcc hold time t dwn 0ms t osc1 t bmv t dwn vcc auto-program mode auto-erase mode figure 6.20 oscillation stabilization time, boot program transfer time, and power-down sequence
rev. 4.00, 05/03, page 174 of 562 6.10.9 notes on memory programming 1. when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. 2. the flash memory is initially in the erased state when the device is shipped by renesas technology. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 6.11 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to at high speed. ? power-down operating mode the power supply circuit of the flash memory is partly halted and can be read under low power consumption. ? standby mode all flash memory circuits are halted. table 6.23 shows the correspondence between the operating modes of this lsi and the flash memory. in subactive mode, the flash memory can be set to operate in power-down mode with the pdwnd bit in flpwcr. when the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in syscr1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. table 6.23 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode watch mode standby mode standby mode
rev. 4.00, 05/03, page 175 of 562 section 7 ram 7.1 overview the h8/38024, h8/38023, h8/38022, h8/38024s, h8/38023s, and h8/38022s have 1 kbyte of high-speed static ram on-chip, and the h8/38021, h8/38020, h8/38021s, and h8/38020s have 512 bytes. the ram is connected to the cpu by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 block diagram figure 7.1 shows a block diagram of the on-chip ram. hff7e hff7f internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address hff7e hfb82 hfb80 hfb80 hfb82 hfb81 hfb83 on-chip ram figure 7.1 ram block diagram (h8/38024)
rev. 4.00, 05/03, page 176 of 562
rev. 4.00, 05/03, page 177 of 562 section 8 i/o ports 8.1 overview the lsi is provided with five 8-bit i/o ports, two 4-bit i/o ports, one 3-bit i/o port, one 8-bit input-only port, one 1-bit input-only port, and one 6-bit output-only port. table 8.1 indicates the functions of each port. each port has of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be assigned to individual bits. see section 2.9.2, notes on bit manipulation, for information on executing bit-manipulation instructions to write data in pcr or pdr. ports 5, 6, 7, 8, and a are also used as liquid crystal display segment and common pins, selectable in 4-bit units. block diagrams of each port are given in appendix c, i/o port block diagrams. table 8.1 port functions port description pins other functions function switching registers port 1 p1 7 / irq 3 /tmif external interrupt 3, timer event input pin tmif pmr1 tcrf p1 6 none p1 4 / irq 4 / adtrg external interrupt 4, a/d converter external trigger pmr1 amr ? 4-bit i/o port ? mos input pull-up option p1 3 /tmig timer g input capture pmr1 pmr2 port 3 p3 7 /aevl p3 6 /aevh asynchronous counter event inputs aevl, aevh pmr3 eccr p3 5 to p3 3 none p3 2 , tmofh p3 1 , tmofl timer f output compare output pmr3 ? 8-bit i/o port ? mos input pull-up option ? large-current port * 1 ? mos open drain output selectable (only p3 5 ) p3 0 /ud timer c count up/down selection input pmr3
rev. 4.00, 05/03, page 178 of 562 port description pins other functions function switching registers port 4 p4 3 / irq 0 external interrupt 0 pmr2 ? 1-bit input port ? 3-bit i/o port p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 sci3 data output (txd 32 ), data input (rxd 32 ), clock input/output (sck 32 ) scr3 smr3 spcr port 5 ? 8-bit i/o port ? mos input pull-up option p5 7 to p5 0 / wkp 7 to wkp 0 / seg 8 to seg 1 wakeup input ( wkp 7 to wkp 0 ), segment output (seg 8 to seg 1 ) pmr5 lpcr port 6 ? 8-bit i/o port ? mos input pull-up option p6 7 to p6 0 / seg 16 to seg 9 segment output (seg 16 to seg 9 ) lpcr port 7 ? 8-bit i/o port p7 7 to p7 0 / seg 24 to seg 17 segment output (seg 24 to seg 17 ) lpcr port 8 ? 8-bit i/o port p8 7 to p8 0 / seg 32 to seg 25 segment output (seg 32 to seg 25 ) lpcr port 9 p9 5 to p9 2 none ? 6-bit output port ? high-voltage, large- current port * 2 p9 1 , p9 0 / pwm2, pwm1 10-bit pwm output pmr9 ? high-voltage port * 2 irqaec none port a 4-bit i/o port pa 3 to pa 0 / com 4 to com 1 common output (com 4 to com 1 ) lpcr port b 8-bit input port pb 7 to pb 4 / an 7 to an 4 a/d converter analog input (an 7 to an 4 ) amr pb 3 /an 3 / irq 1 / tmic a/d converter analog input (an 3 ), external interrupt 1, timer event input (tmic) amr pmrb tmc pb 2 to pb 0 / an 2 to an 0 a/d converter analog input (an 2 to an 0 ) amr notes: * 1 applies to the hd64338024, hd64338023, hd64338022, hd64338021, hd64338020, and hd64738024 only. * 2 standard voltage on h8/38024s group.
rev. 4.00, 05/03, page 179 of 562 8.2 port 1 8.2.1 overview port 1 is a 4-bit i/o port. figure 8.1 shows its pin configuration. p1 7 / 3 /tmif p1 6 p1 4 / 4 / p1 3 /tmig port 1 figure 8.1 port 1 pin configuration 8.2.2 register configuration and description table 8.2 shows the port 1 register configuration. table 8.2 port 1 registers name abbr. r/w initial value address port data register 1 pdr1 r/w h'ffd4 port control register 1 pcr1 w h'ffe4 port pull-up control register 1 pucr1 r/w h'ffe0 port mode register 1 pmr1 r/w h'ffc8 port mode register 2 pmr2 r/w h'd8 h'ffc9
rev. 4.00, 05/03, page 180 of 562 1. port data register 1 (pdr1) bit 76543210 p1 7 p1 6 p1 4 p1 3 initial value 0 0 0 0 read/write r/w r/w r/w r/w pdr1 is an 8-bit register that stores data for port 1 pins p1 7 , p1 6 , p1 4 , and p1 3 . if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are read, regardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. 2. port control register 1 (pcr1) bit 76543210 pcr1 7 pcr1 6 pcr1 4 pcr1 3 initial value 0 0 0 0 read/write wwwwwwww pcr1 is an 8-bit register for controlling whether each of the port 1 pins p1 7 , p1 6 , p1 4 , and p1 3 functions as an input pin or output pin. setting a pcr1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr1 and in pdr1 are valid only when the corresponding pin is designated in pmr1 as a general i/o pin. pcr1 is a write-only register, which is always read as all 1s.
rev. 4.00, 05/03, page 181 of 562 3. port pull-up control register 1 (pucr1) bit 76543210 pucr1 7 pucr1 6 pucr1 4 pucr1 3 initial value 0 0 0 0 read/write r/w r/w w r/w r/w w w w pucr1 controls whether the mos pull-up of each of the port 1 pins p1 7 , p1 6 , p1 4 , and p1 3 is on or off. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. 4. port mode register 1 (pmr1) bit 76543210 irq3 irq4 tmig initial value 0 1 0 0 1 read/write r/w w r/w r/w w w pmr1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. bit 7: p1 7 / irq 3 /tmif pin function switch (irq3) this bit selects whether pin p1 7 / irq 3 /tmif is used as p1 7 or as irq 3 /tmif. bit 7 irq3 description 0 functions as p1 7 i/o pin (initial value) 1 functions as irq 3 /tmif input pin note: rising or falling edge sensing can be designated for irq 3 , tmif. for details on tmif settings, see 3. timer control register f (tcrf) in section 9.4.2. bit 6: reserved bit this bit is reserved; it is always read as 1 and cannot be modified. bit 5: reserved bit this bit is reserved; it can only be written with 0.
rev. 4.00, 05/03, page 182 of 562 bit 4: p1 4 / irq 4 / adtrg pin function switch (irq4) this bit selects whether pin p1 4 / irq 4 / adtrg is used as p1 4 or as irq 4 / adtrg . bit 4 irq4 description 0 functions as p1 4 i/o pin (initial value) 1 functions as irq 4 / adtrg input pin note: for details of adtrg pin setting, see section 12.3.2, start of a/d conversion by external trigger input. bit 3: p1 3 /tmig pin function switch (tmig) this bit selects whether pin p1 3 /tmig is used as p1 3 or as tmig. bit 3 tmig description 0 functions as p1 3 i/o pin (initial value) 1 functions as tmig input pin bits 2 and 0: reserved bits these bits are reserved; they can only be written with 0. bit 1: reserved bit this bit is reserved; it is always read as 1 and cannot be modified. 5. port mode register 2 (pmr2) bit 76543210 pof1 wdcks ncs irq0 initial value11011000 read/write r/w r/w r/w r/w pmr2 is an 8-bit read/write register. it controls whether the pmos transistor internal to p3 5 is on or off, the selection of the watchdog timer clock, the selection of tmig noise cancellation, and switching of the p4 3 / irq 0 pin functions. upon reset, pmr2 is initialized to h'd8. this section only deals with the bits related to timer g and the watchdog timer. for the functions of the bits, see the descriptions of port 3 (pof1) and port 4 (irq0).
rev. 4.00, 05/03, page 183 of 562 bit 2: watchdog timer source clock (wdcks) this bit selects the watchdog timer source clock. bit 2 wdcks description 0 selects /8192 (initial value) 1 selects w /32 bit 1: tmig noise canceller select (ncs) this bit selects controls the noise cancellation circuit of the input capture input signal (tmig). bit 1 ncs description 0 no noise cancellation circuit (initial value) 1 noise cancellation circuit
rev. 4.00, 05/03, page 184 of 562 8.2.3 pin functions table 8.3 shows the port 1 pin functions. table 8.3 port 1 pin functions pin pin functions and selection method p1 7 / irq 3 /tmif the pin function depends on bit irq3 in pmr1, bits cksl2 to cksl0 in tcrf, and bit pcr1 7 in pcr1. irq 3 01 pcr1 7 01 * cksl2 to cksl0 * not 0 ** 0 ** pin function p1 7 input pin p1 7 output pin irq 3 input pin irq 3 /tmif input pin note: when this pin is used as the tmif input pin, clear bit ien3 to 0 in ienr1 to disable the irq 3 interrupt. p1 6 the pin function depends on bit pcr1 6 in pcr1. pcr1 6 01 pin function p1 6 input pin p1 6 output pin p1 4 / irq 4 adtrg the pin function depends on bit irq4 in pmr1, bit trge in amr, and bit pcr1 4 in pcr1. irq4 0 1 pcr1 4 01 * trge * 01 pin function p1 4 input pin p1 4 output pin irq 4 input pin irq 4 / adtrg input pin note: when this pin is used as the adtrg input pin, clear bit ien4 to 0 in ienr1 to disable the irq 4 interrupt. p1 3 /tmig the pin function depends on bit tmig in pmr1 and bit pcr1 3 in pcr1. tmig 0 1 pcr1 3 01 * pin function p1 3 input pin p1 3 output pin tmig input pin * : dont care
rev. 4.00, 05/03, page 185 of 562 8.2.4 pin states table 8.4 shows the port 1 pin states in each operating mode. table 8.4 port 1 pin states pins reset sleep subsleep standby watch subactive active p1 7 / irq 3 /tmif p1 6 p1 4 / irq 4 / adtrg p1 3 /tmig high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.2.5 mos input pull-up port 1 has a built-in mos input pull-up function that can be controlled by software. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset. pcr1 n 001 pucr1 n 01 * mos input pull-up off on off (n = 7, 6, 4, 3) * : dont care
rev. 4.00, 05/03, page 186 of 562 8.3 port 3 8.3.1 overview port 3 is an 8-bit i/o port, configured as shown in figure 8.2. p3 /aevl p3 /aevh p3 7 6 5 port 3 p3 p3 p3 /tmofh 4 3 2 p3 /tmofl 1 p3 /ud 0 figure 8.2 port 3 pin configuration 8.3.2 register configuration and description table 8.5 shows the port 3 register configuration. table 8.5 port 3 registers name abbr. r/w initial value address port data register 3 pdr3 r/w h'00 h'ffd6 port control register 3 pcr3 w h'00 h'ffe6 port pull-up control register 3 pucr3 r/w h'00 h'ffe1 port mode register 2 pmr2 r/w h'd8 h'ffc9 port mode register 3 pmr3 r/w h'ffca
rev. 4.00, 05/03, page 187 of 562 1. port data register 3 (pdr3) bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 0 r/w 2 p3 0 r/w 1 p3 0 r/w 21 54 76 3 pdr3 is an 8-bit register that stores data for port 3 pins p3 7 to p3 0 . if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, regardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. upon reset, pdr3 is initialized to h'00. 2. port control register 3 (pcr3) bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 0 w 2 pcr3 0 w 1 pcr3 0 w 21 54 3 76 pcr3 is an 8-bit register for controlling whether each of the port 3 pins p3 7 to p3 0 functions as an input pin or output pin. setting a pcr3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid only when the corresponding pin is designated in pmr3 as a general i/o pin. upon reset, pcr3 is initialized to h'00. pcr3 is a write-only register, which is always read as all 1s. 3. port pull-up control register 3 (pucr3) bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 2 1 5 43 76 pucr3 controls whether the mos pull-up of each of the port 3 pins p3 7 to p3 0 is on or off. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr3 is initialized to h'00.
rev. 4.00, 05/03, page 188 of 562 4. port mode register 2 (pmr2) bit 76543210 pof1 wdcks ncs irq0 initial value11011000 read/write r/w r/w r/w r/w pmr2 is an 8-bit read/write register. it controls whether the pmos transistor internal to p3 5 is on or off, the selection of the watchdog timer clock, the selection of tmig noise cancellation, and switching of the p4 3 / irq 0 pin functions. upon reset, pmr2 is initialized to h'd8. this section only deals with the bit that controls whether the pmos transistor internal to pin p3 5 is on or off. for the functions of the other bits, see the descriptions of port 1 (wdcks and ncs) and port 4 (irq0). bit 5: pin p3 5 pmos transistor control (pof1) this bit selects whether the pmos transistor of the output buffer for pin p3 5 is on or off. bit 5 pof1 description 0 cmos output (initial value) 1 nmos open-drain output note: the pin is an nmos open-drain output when this bit is set to 1 and p3 5 is an output.
rev. 4.00, 05/03, page 189 of 562 5. port mode register 3 (pmr3) bit initial value read/write 7 aevl 0 r/w 6 aevh 0 r/w 5 w 4 w 3 w 0 ud 0 r/w 2 tmofh 0 r/w 1 tmofl 0 r/w pmr3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. bit 7: p3 7 /aevl pin function switch (aevl) this bit selects whether pin p3 7 /aevl is used as p3 7 or as aevl. bit 7 aevl description 0 functions as p3 7 i/o pin (initial value) 1 functions as aevl input pin bit 6: p3 6 /aevh pin function switch (aevh) this bit selects whether pin p3 6 /aevh is used as p3 6 or as aevh. bit 6 aevh description 0 functions as p3 6 i/o pin (initial value) 1 functions as aevh input pin bits 5 to 3: reserved bits these bits are reserved; they can only be written with 0. bit 2: p3 2 /tmofh pin function switch (tmofh) this bit selects whether pin p3 2 /tmofh is used as p3 2 or as tmofh. bit 2 tmofh description 0 functions as p3 2 i/o pin (initial value) 1 functions as tmofh output pin
rev. 4.00, 05/03, page 190 of 562 bit 1: p3 1 /tmofl pin function switch (tmofl) this bit selects whether pin p3 1 /tmofl is used as p3 1 or as tmofl. bit 1 tmofl description 0 functions as p3 1 i/o pin (initial value) 1 functions as tmofl output pin bit 0: p3 0 /ud pin function switch (ud) this bit selects whether pin p3 0 /ud is used as p3 0 or as ud. bit 0 ud description 0 functions as p3 0 i/o pin (initial value) 1 functions as ud input pin
rev. 4.00, 05/03, page 191 of 562 8.3.3 pin functions table 8.6 shows the port 3 pin functions. table 8.6 port 3 pin functions pin pin functions and selection method p3 7 /aevl the pin function depends on bit aevl in pmr3 and bit pcr3 7 in pcr3. aevl 0 1 pcr3 7 01 * pin function p3 7 input pin p3 7 output pin aevl input pin p3 6 /aevh the pin function depends on bit aevh in pmr3 and bit pcr3 6 in pcr3. aevh 0 1 pcr3 6 01 * pin function p3 6 input pin p3 6 output pin aevh input pin p3 5 to p3 3 the pin function depends on the corresponding bit in pcr3. pcr3n 0 1 pin function p3 n input pin p3 n output pin (n = 5 to 3) p3 2 /tmofh the pin function depends on bit tmofh in pmr3 and bit pcr3 2 in pcr3. tmofh 0 1 pcr3 2 01 * pin function p3 2 input pin p3 2 output pin tmofh output pin p3 1 /tmofl the pin function depends on bit tmofl in pmr3 and bit pcr3 1 in pcr3. tmofl 0 1 pcr3 1 01 * pin function p3 1 input pin p3 1 output pin thofl output pin p3 0 /ud the pin function depends on bit ud in pmr3 and bit pcr30 in pcr3. ud 0 1 pcr3 0 01 * pin function p3 0 input pin p3 0 output pin ud input pin * : dont care
rev. 4.00, 05/03, page 192 of 562 8.3.4 pin states table 8.7 shows the port 3 pin states in each operating mode. table 8.7 port 3 pin states pins reset sleep subsleep standby watch subactive active p3 7 /aevl p3 6 /aevh p3 5 p3 4 p3 3 p3 2 /tmofh p3 1 /tmofl p3 0 /ud high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.3.5 mos input pull-up port 3 has a built-in mos input pull-up function that can be controlled by software. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr3 n 001 pucr3 n 01 * mos input pull-up off on off (n = 7 to 0) * : dont care
rev. 4.00, 05/03, page 193 of 562 8.4 port 4 8.4.1 overview port 4 is a 3-bit i/o port and 1-bit input port, configured as shown in figure 8.3. p4 p4 p4 p4 / 0 /txd 32 /rxd 32 /sck 32 3 2 1 0 port 4 figure 8.3 port 4 pin configuration 8.4.2 register configuration and description table 8.8 shows the port 4 register configuration. table 8.8 port 4 registers name abbr. r/w initial value address port data register 4 pdr4 r/w h'f8 h'ffd7 port control register 4 pcr4 w h'f8 h'ffe7 port mode register 2 pmr2 r/w h'd8 h'ffc9 1. port data register 4 (pdr4) ) 9 / / / / h )) / a )) a 9 n )) a 9 / )) a 9 hn/a pdr4 is an 8-bit register that stores data for port 4 pins p4 2 to p4 0 . if port 4 is read while pcr4 bits are set to 1, the values stored in pdr4 are read, regardless of the actual pin states. if port 4 is read while pcr4 bits are cleared to 0, the pin states are read. upon reset, pdr4 is initialized to h'f8.
rev. 4.00, 05/03, page 194 of 562 2. port control register 4 (pcr4) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w 210 pcr4 is an 8-bit register for controlling whether each of port 4 pins p4 2 to p4 0 functions as an input pin or output pin. setting a pcr4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr4 and pdr4 settings are valid when the corresponding pins are designated for general-purpose input/output by scr3. upon reset, pcr4 is initialized to h'f8. pcr4 is a write-only register, which is always read as all 1s. 3. port mode register 2 (pmr2) bit initial value read/write 7 1 6 1 5 pof1 0 r/w 4 1 3 1 0 irq 0 0 r/w 2 wdcks 0 r/w 1 ncs 0 r/w pmr2 is an 8-bit read/write register. it controls whether the pmos transistor internal to p3 5 is on or off, the selection of the watchdog timer clock, the selection of tmig noise cancellation, and switching of the p4 3 / irq 0 pin functions. upon reset, pmr2 is initialized to h'd8. this section only deals with the bit that controls switching of the p4 3 / irq 0 pin functions. for the functions of the other bits, see the descriptions of port 1 (wdcks and ncs) and port 3 (pof1). bit 0: p4 3 / irq 0 pin function switch (irq 0 ) this bit selects whether pin p4 3 / irq 0 is used as p4 3 or as irq 0 . bit 0 irq 0 description 0 functions as p4 3 input pin (initial value) 1 functions as irq 0 input pin
rev. 4.00, 05/03, page 195 of 562 8.4.3 pin functions table 8.9 shows the port 4 pin functions. table 8.9 port 4 pin functions pin pin functions and selection method p4 3 / irq 0 the pin function depends on bit irq0 in pmr2. irq0 0 1 pin function p4 3 input pin irq 0 input pin p4 2 /txd 32 the pin function depends on bit te in scr3, bit spc32 in spcr, and bit pcr4 2 in pcr4. spc32 0 1 te 0 1 pcr4 2 01 * pin function p4 2 input pin p4 2 output pin txd 32 output pin p4 1 /rxd 32 the pin function depends on bit re in scr3 and bit pcr4 1 in pcr4. re 0 1 pcr4 1 01 * pin function p4 1 input pin p4 1 output pin rxd 32 input pin p4 0 /sck 32 the pin function depends on bit cke1 and cke0 in scr3, bit com in smr3, and bit pcr4 0 in pcr4. cke1 0 1 cke0 0 1 * com 0 1 ** pcr4 0 01 ** pin function p4 0 input pin p4 0 output pin sck 32 output pin sck 32 input pin * : dont care
rev. 4.00, 05/03, page 196 of 562 8.4.4 pin states table 8.10 shows the port 4 pin states in each operating mode. table 8.10 port 4 pin states pins reset sleep subsleep standby watch subactive active p4 3 / irq 0 p4 2 /txd 32 p4 1 /rxd 32 p4 0 /sck 32 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
rev. 4.00, 05/03, page 197 of 562 8.5 port 5 8.5.1 overview port 5 is an 8-bit i/o port, configured as shown in figure 8.4. p5 7 / 7 /seg 8 p5 6 / 6 /seg 7 p5 5 / 5 /seg 6 p5 4 / 4 /seg 5 p5 3 / 3 /seg 4 p5 2 / 2 /seg 3 p5 1 / 1 /seg 2 p5 0 / 0 /seg 1 port 5 figure 8.4 port 5 pin configuration 8.5.2 register configuration and description table 8.11 shows the port 5 register configuration. table 8.11 port 5 registers name abbr. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd8 port control register 5 pcr5 w h'00 h'ffe8 port pull-up control register 5 pucr5 r/w h'00 h'ffe2 port mode register 5 pmr5 r/w h'00 h'ffcc
rev. 4.00, 05/03, page 198 of 562 1. port data register 5 (pdr5) bit 76543210 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdr5 is an 8-bit register that stores data for port 5 pins p5 7 to p5 0 . if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. upon reset, pdr5 is initialized to h'00. 2. port control register 5 (pcr5) bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w 76543210 pcr5 is an 8-bit register for controlling whether each of the port 5 pins p5 7 to p5 0 functions as an input pin or output pin. setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr5 and pdr5 settings are valid when the corresponding pins are designated for general-purpose input/output by pmr5 and bits sgs3 to sgs0 in lpcr. upon reset, pcr5 is initialized to h'00. pcr5 is a write-only register, which is always read as all 1s. 3. port pull-up control register 5 (pucr5) bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 76543210 pucr5 controls whether the mos pull-up of each of port 5 pins p5 7 to p5 0 is on or off. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr5 is initialized to h'00.
rev. 4.00, 05/03, page 199 of 562 4. port mode register 5 (pmr5) bit 76543210 wkp 7 wkp 6 wkp 5 wkp 4 wkp 3 wkp 2 wkp 1 wkp 0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pmr5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. upon reset, pmr5 is initialized to h'00. bit n: p5 n / wkp n /seg n+1 pin function switch (wkpn) when pin p5n/ wkp n/segn+1 is not used as seg n+1 , these bits select whether the pin is used as p5n or wkp n . bit n wkpn description 0 functions as p5n i/o pin (initial value) 1 functions as wkp n input pin (n = 7 to 0) note: for use as seg n+1 , see section 13.2.1, lcd port control register (lpcr).
rev. 4.00, 05/03, page 200 of 562 8.5.3 pin functions table 8.12 shows the port 5 pin functions. table 8.12 port 5 pin functions pin pin functions and selection method p5 7 / wkp 7 / seg 8 to the pin function depends on bits wkp 7 to wkp 0 in pmr5, bits pcr5 7 to pcr5 0 in pcr5, and bits sgs3 to sgs0 in lpcr. p5 0 / wkp 0 / seg 1 p5 7 to p5 4 (n = 7 to 4) sgs3 to sgs0 other than 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001 wkp n 01 * pcr5 n 01 ** pin function p5 n input pin p5 n output pin wkpn input pin segn+1 output pin p5 3 to p5 0 (m= 3 to 0) sgs3 to sgs0 other than 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000 wkp m 01 * pcr5 m 01 ** pin function p5 m input pin p5 m output pin wkpm output pin segm+1 output pin * : dont care
rev. 4.00, 05/03, page 201 of 562 8.5.4 pin states table 8.13 shows the port 5 pin states in each operating mode. table 8.13 port 5 pin states pins reset sleep subsleep standby watch subactive active p5 7 / wkp 7 / seg 8 to p5 0 / wkp 0 /seg 1 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. in the hd64f38024 the previous pin state is retained. 8.5.5 mos input pull-up port 5 has a built-in mos input pull-up function that can be controlled by software. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr5 n 001 pucr5 n 01 * mos input pull-up off on off (n = 7 to 0) * : dont care
rev. 4.00, 05/03, page 202 of 562 8.6 port 6 8.6.1 overview port 6 is an 8-bit i/o port. the port 6 pin configuration is shown in figure 8.5. p6 7 /seg 16 p6 6 /seg 15 p6 5 /seg 14 p6 4 /seg 13 p6 3 /seg 12 p6 2 /seg 11 p6 1 /seg 10 p6 0 /seg 9 port 6 figure 8.5 port 6 pin configuration 8.6.2 register configuration and description table 8.14 shows the port 6 register configuration. table 8.14 port 6 registers name abbr. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd9 port control register 6 pcr6 w h'00 h'ffe9 port pull-up control register 6 pucr6 r/w h'00 h'ffe3
rev. 4.00, 05/03, page 203 of 562 1. port data register 6 (pdr6) bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 210 54 76 3 pdr6 is an 8-bit register that stores data for port 6 pins p6 7 to p6 0 . if port 6 is read while pcr6 bits are set to 1, the values stored in pdr6 are read, regardless of the actual pin states. if port 6 is read while pcr6 bits are cleared to 0, the pin states are read. upon reset, pdr6 is initialized to h'00. 2. port control register 6 (pcr6) bit initial value read/write 7 pcr6 7 0 w 6 pcr6 6 0 w 5 pcr6 5 0 w 4 pcr6 4 0 w 3 pcr6 3 0 w 0 pcr6 0 0 w 2 pcr6 2 0 w 1 pcr6 1 0 w pcr6 is an 8-bit register for controlling whether each of the port 6 pins p6 7 to p6 0 functions as an input pin or output pin. setting a pcr6 bit to 1 makes the corresponding pin (p6 7 to p6 0 ) an output pin, while clearing the bit to 0 makes the pin an input pin. pcr6 and pdr6 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr6 is initialized to h'00. pcr6 is a write-only register, which is always read as all 1s.
rev. 4.00, 05/03, page 204 of 562 3. port pull-up control register 6 (pucr6) bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 2 10 5 43 76 pucr6 controls whether the mos pull-up of each of the port 6 pins p6 7 to p6 0 is on or off. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr6 is initialized to h'00. 8.6.3 pin functions table 8.15 shows the port 6 pin functions. table 8.15 port 6 pin functions pin pin functions and selection method p6 7 /seg 16 to p6 0 /seg 9 the pin function depends on bits pcr6 7 to pcr6 0 in pcr6 and bits sgs3 to sgs0 in lpcr. p6 7 to p6 4 (n = 7 to 4) sgs3 to sgs0 other than 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011 pcr6 n 01 * pin function p6 n input pin p6 n output pin seg n+9 output pin p6 3 to p6 0 (m = 3 to 0) sgs3 to sgs0 other than 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010 pcr6 m 01 * pin function p6 m input pin p6 m output pin seg m+9 output pin * : dont care
rev. 4.00, 05/03, page 205 of 562 8.6.4 pin states table 8.16 shows the port 6 pin states in each operating mode. table 8.16 port 6 pin states pin reset sleep subsleep standby watch subactive active p6 7 /seg 16 to p6 0 /seg 9 high- impedance retains previous state retains previous state high- impedance * retains previous state functional functional note: * a high-level signal is output when the mos pull-up is in the on state. 8.6.5 mos input pull-up port 6 has a built-in mos pull-up function that can be controlled by software. when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr6 n 001 pucr6 n 01 * mos input pull-up off on off (n = 7 to 0) * : dont care
rev. 4.00, 05/03, page 206 of 562 8.7 port 7 8.7.1 overview port 7 is an 8-bit i/o port, configured as shown in figure 8.6. p7 7 /seg 24 p7 6 /seg 23 p7 5 /seg 22 p7 4 /seg 21 p7 3 /seg 20 port 7 p7 2 /seg 19 p7 1 /seg 18 p7 0 /seg 17 figure 8.6 port 7 pin configuration 8.7.2 register configuration and description table 8.17 shows the port 7 register configuration. table 8.17 port 7 registers name abbr. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffda port control register 7 pcr7 w h'00 h'ffea
rev. 4.00, 05/03, page 207 of 562 1. port data register 7 (pdr7) bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 76543210 pdr7 is an 8-bit register that stores data for port 7 pins p7 7 to p7 0 . if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read. upon reset, pdr7 is initialized to h'00. 2. port control register 7 (pcr7) bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w 76543210 pcr7 is an 8-bit register for controlling whether each of the port 7 pins p7 7 to p7 0 functions as an input pin or output pin. setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr7 and pdr7 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr7 is initialized to h'00. pcr7 is a write-only register, which is always read as all 1s.
rev. 4.00, 05/03, page 208 of 562 8.7.3 pin functions table 8.18 shows the port 7 pin functions. table 8.18 port 7 pin functions pin pin functions and selection method p7 7 /seg 24 to p7 0 /seg 17 the pin function depends on bits pcr7 7 to pcr7 0 in pcr7 and bits sgs3 to sgs0 in lpcr. p7 7 to p7 4 (n = 7 to 4) sgs3 to sgs0 other than 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101 pcr7 n 01 * pin function p7 n input pin p7 n output pin seg n+17 output pin p7 3 to p7 0 (m = 3 to 0) sgs3 to sgs0 other than 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100 pcr7 m 01 * pin function p7 m input pin p7 m output pin seg m+17 output pin * : dont care 8.7.4 pin states table 8.19 shows the port 7 pin states in each operating mode. table 8.19 port 7 pin states pins reset sleep subsleep standby watch subactive active p7 7 /seg 24 to p7 0 /seg 17 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
rev. 4.00, 05/03, page 209 of 562 8.8 port 8 8.8.1 overview port 8 is an 8-bit i/o port configured as shown in figure 8.7. p8 7 /seg 32 p8 6 /seg 31 p8 5 /seg 30 p8 4 /seg 29 p8 3 /seg 28 p8 2 /seg 27 p8 1 /seg 26 p8 0 /seg 25 port 8 figure 8.7 port 8 pin configuration 8.8.2 register configuration and description table 8.20 shows the port 8 register configuration. table 8.20 port 8 registers name abbr. r/w initial value address port data register 8 pdr8 r/w h'00 h'ffdb port control register 8 pcr8 w h'00 h'ffeb
rev. 4.00, 05/03, page 210 of 562 1. port data register 8 (pdr8) bit initial value read/write 7 p8 7 0 r/w 6 p8 6 0 r/w 5 p8 5 0 r/w 4 p8 4 0 r/w 3 p8 3 0 r/w 0 p8 0 r/w 2 p8 2 0 r/w 1 p8 1 0 r/w 0 pdr8 is an 8-bit register that stores data for port 8 pins p8 7 to p8 0 . if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. upon reset, pdr8 is initialized to h'00. 2. port control register 8 (pcr8) bit initial value read/write 7 pcr8 7 0 w 6 pcr8 6 0 w 5 pcr8 5 0 w 4 pcr8 4 0 w 3 pcr8 3 0 w 0 pcr8 0 0 w 2 pcr8 2 0 w 1 pcr8 1 0 w pcr8 is an 8-bit register for controlling whether the port 8 pins p8 7 to p8 0 functions as an input or output pin. setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcr8 and pdr8 settings are valid when the corresponding pins are designated for general-purpose input/output by bits sgs3 to sgs0 in lpcr. upon reset, pcr8 is initialized to h'00. pcr8 is a write-only register, which is always read as all 1s.
rev. 4.00, 05/03, page 211 of 562 8.8.3 pin functions table 8.21 shows the port 8 pin functions. table 8.21 port 8 pin functions pin pin functions and selection method the pin function depends on bits pcr8 7 to pcr8 0 in pcr8 and bits sgs3 to sgs0 in lpcr. p8 7 to p8 4 (n = 7 to 4) p8 7 /seg 32 to p8 0 /seg 25 sgs3 to sgs0 other than 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 pcr8 n 01 * pin function p8 n input pin p8 n output pin seg n+25 output pin p8 3 to p8 0 (m = 3 to 0) sgs3 to sgs0 other than 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 pcr8 m 01 * pin function p8 m input pin p8 m output pin seg m+25 output pin * : dont care 8.8.4 pin states table 8.22 shows the port 8 pin states in each operating mode. table 8.22 port 8 pin states pins reset sleep subsleep standby watch subactive active p8 7 /seg 32 to p8 0 /seg 25 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
rev. 4.00, 05/03, page 212 of 562 8.9 port 9 8.9.1 overview port 9 is a 6-bit output port, configured as shown in figure 8.8. p9 5 p9 4 p9 3 p9 2 p9 1 /pwm 2 p9 0 /pwm 1 port 9 figure 8.8 port 5 pin configuration 8.9.2 register configuration and description table 8.23 shows the port 9 register configuration. table 8.23 port 9 registers name abbr. r/w initial value address port data register 9 pdr9 r/w h'ff h'ffdc port mode register 9 pmr9 r/w h'ffec 1. port data register 9 (pdr9) bit initial value read/write 7 ? 1 ? 6 ? 1 ? 5 p9 1 r/w 4 p9 1 r/w 3 p9 1 r/w 0 p9 1 r/w 2 p9 1 r/w 1 p9 1 r/w 543210 pdr9 is an 8-bit register that stores data for port 9 pins p9 5 to p9 0 . upon reset, pdr9 is initialized to h'ff.
rev. 4.00, 05/03, page 213 of 562 2. port mode register 9 (pmr9) pmr9 is an 8-bit read/write register controlling the selection of the p9 0 and p9 1 pin functions. bit 3: p9 2 to p9 0 step-up circuit control (pioff) bit 3 turns the p9 2 to p9 0 step-up circuit on and off. this bit is reserved in the h8/38024s group. bit 3 pioff description 0 large-current port step-up circuit is turned on (initial value) 1 large-current port step-up circuit is turned off note: in the h8/38024 ztat version and mask rom version, and the hd64f38024r, the following precautions should be followed when accessing the pioff bit. when turning the voltage boost circuit on or off, always write to the register when the buffer nmos is off (port data set to 1). also, when turning on the voltage boost circuit, first clear pioff to 0 and then after waiting 30 system clock cycles turn on the buffer nmos (port data cleared to 0). if 30 system clock cycles have not elapsed the voltage boost circuit will not start operating and it will not be possible to produce a large current flow, resulting in unstable operation. in the hd64f38024, the following precautions should be followed when accessing the pioff bit. in the hd64f38024, if port data bits are cleared from 1 to 0 while the pioff bit is set to 1, repeated charge-discharge cycles will occur in the voltage boost circuit, causing the current consumption to rise and fall cyclically. the amount of rise in the current consumption in this case is between several tens of a and 100 a above the normal level. therefore, the following points should be kept in mind. (1)not using subclock regardless of whether or not port 9 is used, the pioff bit should be left at its initial value (0) and not changed. (2)not using port 9 port data should be used unchanged with the pioff bit either at its initial value (0) or set to 1. in the latter case the current consumption will vary, due to the intermittent operation of the voltage boost circuit, by about 1 a (standby mode or watch mode, v cc = 3.0 v, ta = 25 c).
rev. 4.00, 05/03, page 214 of 562 (3) using port 9 with pioff always cleared to 0 this case applies to instances in which the voltage boost circuit is used constantly to generate a large current glow, or an increase in current consumption due to the operation of the voltage boost circuit is permissible even in the standby mode or watch mode (see (2) above). in this case the pioff bit should be left at its initial value (0) and not changed. (4) using port 9 with pioff set to 1 this case applies to instances in which it is necessary to change the value of the pioff bit due to operating conditions or where it is desirable to keep the pioff bit set to 1 because no large current is required (for example, shutting down the voltage boost circuit to reduce current consumption in the watch mode). in this case, clear port data from 1 to 0 only when the pioff bit is cleared to 0. also, if a large current flow is required, the pioff bit should be set to 1 and all the port data bits set to 1. then clear pioff to 0 and, after allowing 30 clock cycles to permit stabilization of the voltage boost circuit, clear the port data bits to 0. if time is not provided to allow the voltage boost circuit to stabilize, it will not be possible to produce a large current flow. there are no such restrictions when setting port data bits from 0 to 1, regardless of the size of the current flow. to shut down the voltage boost circuit, set pioff to 1 after programming the port data bits. an example of the sequence of steps is provided below. (example procedure) shutting down the in the watch mode without a large current flow to port 9 other operation pioff = 0 (voltage boost circuit on) pdr9 operation or other operation pioff = 1 (voltage boost circuit off) execute sleep instruction watch mode cancel watch mode bit 2: reserved bit this bit is reserved; it can only be written with 0.
rev. 4.00, 05/03, page 215 of 562 bits 1 and 0: p9 n /pwm pin function switches these pins select whether pin p9n/pwmn+1 is used as p9n or as pwmn+1. bit n wkpn+1 description 0 functions as p9 n output pin (initial value) 1 functions as pwm n+1 output pin (n = 0 or 1) 8.9.3 pin functions table 8.24 shows the port 9 pin functions. table 8.24 port 9 pin functions pin pin functions and selection method (n = 1 or 0) p9 1 /pwm n+1 to p9 0 /pwm n+1 pmr9 n 01 pin function p9 n output pin pwm n+1 output pin 8.9.4 pin states table 8.25 shows the port 9 pin states in each operating mode. table 8.25 port 9 pin states pins reset sleep subsleep standby watch subactive active p9 5 to p9 2 p9 n /pwm n+1 to p9 n /pwm n+1 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional (n = 1 or 0)
rev. 4.00, 05/03, page 216 of 562 8.10 port a 8.10.1 overview port a is a 4-bit i/o port, configured as shown in figure 8.9. pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 port a figure 8.9 port a pin configuration 8.10.2 register configuration and description table 8.26 shows the port a register configuration. table 8.26 port a registers name abbr. r/w initial value address port data register a pdra r/w h'f0 h'ffdd port control register a pcra w h'f0 h'ffed 1. port data register a (pdra) bit initial value read/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 3210 pdra is an 8-bit register that stores data for port a pins pa 3 to pa 0 . if port a is read while pcra bits are set to 1, the values stored in pdra are read, regardless of the actual pin states. if port a is read while pcra bits are cleared to 0, the pin states are read. upon reset, pdra is initialized to h'f0.
rev. 4.00, 05/03, page 217 of 562 2. port control register a (pcra) bit initial value read/write 7 1 6 1 5 1 4 1 3 pcra 0 w 0 pcra 0 w 2 pcra 0 w 1 pcra 0 w 3210 pcra controls whether each of port a pins pa 3 to pa 0 functions as an input pin or output pin. setting a pcra bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. pcra and pdra settings are valid when the corresponding pins are designated for general-purpose input/output by lpcr. upon reset, pcra is initialized to h'f0. pcra is a write-only register, which is always read as all 1s.
rev. 4.00, 05/03, page 218 of 562 8.10.3 pin functions table 8.27 shows the port a pin functions. table 8.27 port a pin functions pin pin functions and selection method pa 3 /com 4 the pin function depends on bit pcra 3 in pcra and bits sgs3 to sgs0. sgs3 to sgs0 0000 0000 not 0000 pcra 3 01 * pin function pa 3 input pin pa 3 output pin com 4 output pin pa 2 /com 3 the pin function depends on bit pcra 2 in pcra and bits sgs3 to sgs0. sgs3 to sgs0 0000 0000 not 0000 pcra 2 01 * pin function pa 2 input pin pa 2 output pin com 3 output pin pa 1 /com 2 the pin function depends on bit pcra 1 in pcra and bits sgs3 to sgs0. sgs3 to sgs0 0000 0000 not 0000 pcra 1 01 * pin function pa 1 input pin pa 1 output pin com 2 output pin pa 0 /com 1 the pin function depends on bit pcra 0 in pcra and bits sgs3 to sgs0. sgs3 to sgs0 0000 not 0000 pcra 0 01 * pin function pa 0 input pin pa 0 output pin com 1 output pin * : dont care
rev. 4.00, 05/03, page 219 of 562 8.10.4 pin states table 8.28 shows the port a pin states in each operating mode. table 8.28 port a pin states pins reset sleep subsleep standby watch subactive active pa 3 /com 4 pa 2 /com 3 pa 1 /com 2 pa 0 /com 1 high- impedance retains previous state retains previous state high- impedance retains previous state functional functional
rev. 4.00, 05/03, page 220 of 562 8.11 port b 8.11.1 overview port b is an 8-bit input-only port, configured as shown in figure 8.10. pb 7 /an 7 pb 6 /an 6 pb 5 /an 5 pb 4 /an 4 pb 3 /an 3 / 1 /tmic pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 port b figure 8.10 port b pin configuration 8.11.2 register configuration and description table 8.29 shows the port b register configuration. table 8.29 port b register name abbr. r/w initial value address port data register b pdrb r h'ffde port mode register b pmrb r/w h'f7 h'ffee 1. port data register b (pdrb) bit read/write 7 pb 7 r 6 pb 6 r 5 pb 5 r 4 pb 4 r 3 pb r 0 pb r 2 pb r 1 pb r 32 1 0 reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage.
rev. 4.00, 05/03, page 221 of 562 2. port mode register b (pmrb) bit initial value read/write 7 1 6 1 5 1 4 1 3 irq1 0 r/w 0 1 2 1 1 1 pmrb is an 8-bit read/write register controlling the selection of the pb 3 pin function. upon reset, pmrb is initialized to h'f7. bits 7 to 4 and 2 to 0: reserved bits bits 7 to 4 and 2 to 0 are reserved; they are always read as 1 and cannot be modified. bit 3: pb 3 /an 3 / irq 1 pin function switch (irq1) these bits select whether pin pb 3 /an 3 / irq 1 is used as pb 3 /an 3 or as irq 1 /tmic. bit 3 irq1 description 0 functions as pb 3 /an 3 input pin (initial value) 1 functions as irq 1 /tmic input pin note: rising or falling edge sensing can be selected for the irq 1 /tmic pin. for tmic pin setting, see section 9.3.2 (1), timer mode register c (tmc). 8.11.3 pin functions table 8.30 shows the port b pin functions.
rev. 4.00, 05/03, page 222 of 562 table 8.30 port b pin functions pin pin functions and selection method pb 7 /an 7 the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 not 1011 1011 pin function pb 7 input pin an 7 input pin pb 6 /an 6 the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 not 1010 1010 pin function pb 6 input pin an 6 input pin pb 5 /an 5 the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 not 1001 1001 pin function pb 5 input pin an 5 input pin pb 4 /an 4 the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 not 1000 1000 pin function pb 4 input pin an 4 input pin pb 3 /an 3 / irq 1 / tmic the pin function depends on bits ch3 to ch0 in amr and bit irq1 in pmrb and bits tmc2 to tmc0 in tmc. irq 1 01 ch3 to ch0 not 0111 0111 * tmc2 to tmc0 * not 111 111 pin function pb 3 input pin an 3 input pin irq 1 input pin tmic input pin note: when this pin is used as the tmic input pin, clear ien1 to 0 in ienr1 to disable the irq1 interrupt. pb 2 /an 2 the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 not 0110 0110 pin function pb 2 input pin an 2 input pin pb 1 /an 1 the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 not 0101 not 0000 pin function pb 1 input pin an 1 input pin
rev. 4.00, 05/03, page 223 of 562 pin pin functions and selection method pb 0 /an 0 the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 not 0100 0100 pin function pb 0 input pin an 0 input pin * : dont care 8.12 input/output data inversion function 8.12.1 overview with input pin rxd 32 and output pin txd 32 , the data can be handled in inverted form. scinv2 rxd 32 p4 1 /rxd 32 scinv3 txd 32 p4 2 /txd 32 figure 8.11 input/output data inversion function 8.12.2 register configuration and descriptions table 8.31 shows the registers used by the input/output data inversion function. table 8.31 register configuration name abbr. r/w address serial port control register spcr r/w h'ff91
rev. 4.00, 05/03, page 224 of 562 serial port control register (spcr) bit initial value read/write 7 1 6 1 5 spc32 0 r/w 4 w 3 scinv3 0 r/w 0 w 2 scinv2 0 r/w 1 w spcr is an 8-bit readable/writable register that performs rxd 32 and txd 32 pin input/output data inversion switching. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. bit 4: reserved bit bit 4 is reserved; it can only be written with 0. bit 3: txd 32 pin output data inversion switch bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0txd 32 output data is not inverted (initial value) 1txd 32 output data is inverted
rev. 4.00, 05/03, page 225 of 562 bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted. bit 2 scinv2 description 0rxd 32 input data is not inverted (initial value) 1rxd 32 input data is inverted bits 1 and 0: reserved bits bits 1 and 0 are reserved; they can only be written with 0. 8.12.3 note on modification of serial port control register when a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. when modifying a serial port control register, do so in a state in which data changes are invalidated. 8.13 application note 8.13.1 the management of the un-use terminal if an i/o pin not used by the user system is floating, pull it up or down. ? if an unused pin is an input pin, handle it in one of the following ways: ? pull it up to v cc with an on-chip pull-up mos. ? pull it up to v cc with an external resistor of approximately 100 k ? . ? pull it down to v ss with an external resistor of approximately 100 k ? . ? for a pin also used by the a/d converter, pull it up to av cc . ? if an unused pin is an output pin, handle it in one of the following ways: ? set the output of the unused pin to high and pull it up to v cc with an on-chip pull-up mos. ? set the output of the unused pin to high and pull it up to v cc with an external resistor of approximately 100 k ? . ? set the output of the unused pin to low and pull it down to gnd with an external resistor of approximately 100 k ? .
rev. 4.00, 05/03, page 226 of 562
rev. 4.00, 05/03, page 227 of 562 section 9 timers 9.1 overview the h8/38024 group provides six timers: timers a, c, f, g, and a watchdog timer, and an asynchronous event counter. the functions of these timers are outlined in table 9.1. table 9.1 timer functions name functions internal clock event input pin waveform output pin remarks timer a ? 8-bit timer ? interval function /8 to /8192 (8 choices) ? time base w /128 (choice of 4 overflow periods) timer c ? 8-bit timer ? interval function ? event counting function ? up-count/down-count selectable /4 to /8192, w /4 (7 choices) tmic up-count/ down-count controllable by software or hardware timer f ? 16-bit timer ? event counting function ? also usable as two independent 8-bit timers ? output compare output function /4 to /32, w /4 (4 choices) tmif tmofl tmofh timer g ? 8-bit timer ? input capture function ? interval function /2 to /64, w /4 (4 choices) tmig counter clearing option built-in capture input signal noise canceler watchdog timer ? reset signal generated when 8-bit counter overflows /8192 w /32 asynchro- nous event counter ? 16-bit counter ? also usable as two independent 8-bit counters ? counts events asynchronous to and w ? can count asynchronous events (rising/falling/both edges) independ-ently of the mcu's internal clock /2 to /8 (3 choices) aevl aevh irqaec
rev. 4.00, 05/03, page 228 of 562 9.2 timer a 9.2.1 overview timer a is an 8-bit timer with interval timing and real-time clock time-base functions. the clock time-base function is available when a 32.768 khz crystal oscillator is connected. 1. features features of timer a are given below. ? choice of eight internal clock sources ( /8192, /4096, /2048, /512, /256, /128, /32, /8). ? choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator). ? an interrupt is requested when the counter overflows. ? use of module standby mode enables this module to be placed in standby mode independently when not used.
rev. 4.00, 05/03, page 229 of 562 2. block diagram figure 9.1 shows a block diagram of timer a. w psw internal data bus pss notation: 1/4 tma tca /8192, /4096, /2048, /512, /256, /128, /32, /8 irrta 8 * 64 * 128 * 256 * w /4 w /128 tma: tca: irrta: psw: pss: note: * can be selected only when the prescaler w output ( w /128) is used as the tca input clock. timer mode register a timer counter a timer a overflow interrupt request flag prescaler w prescaler s figure 9.1 block diagram of timer a
rev. 4.00, 05/03, page 230 of 562 3. register configuration table 9.2 shows the register configuration of timer a. table 9.2 timer a registers name abbr. r/w initial value address timer mode register a tma r/w h'ffb0 timer counter a tca r h'00 h'ffb1 clock stop register 1 ckstpr1 r/w h'ff h'fffa 9.2.2 register descriptions 1. timer mode register a (tma) bit initial value read/write 7 w 6 w 5 w 4 1 3 tma3 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w tma is an 8-bit read/write register for selecting the prescaler, and input clock. bits 7 to 5: reserved bits bits 7 to 5 are reserved; only 0 can be written to these bits. bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified.
rev. 4.00, 05/03, page 231 of 562 bits 3 to 0: internal clock select (tma3 to tma0) bits 3 to 0 select the clock input to tca. the selection is made as follows. description bit 3 tma3 bit 2 tma2 bit 1 tma1 bit 0 tma0 prescaler and divider ratio or overflow periodfunction 0000 pss, /8192 (initial value) interval timer 1 pss, /4096 1 0 pss, /2048 1 pss, /512 1 0 0 pss, /256 1 pss, /128 1 0 pss, /32 1 pss, /8 1000psw, 1 s clock time 1 psw, 0.5 s base 1 0 psw, 0.25 s (when using 1 psw, 0.03125 s 32.768 khz) 100psw and tca are reset 1 10 1
rev. 4.00, 05/03, page 232 of 562 2. timer counter a (tca) bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 of tma to 11. upon reset, tca is initialized to h'00. 3. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer a is described here. for details of the other bits, see the sections on the relevant modules. bit 0: timer a module standby mode control (tackstp) bit 0 controls setting and clearing of module standby mode for timer a. tackstp description 0 timer a is set to module standby mode 1 timer a module standby mode is cleared (initial value)
rev. 4.00, 05/03, page 233 of 562 9.2.3 timer operation 1. interval timer operation when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested. * at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see section 3.3, interrupts. 2. real-time clock time base operation when bit tma3 in tma is set to 1, timer a functions as a real-time clock time base by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to their initial values of h'00. 9.2.4 timer a operation states table 9.3 summarizes the timer a operation states. table 9.3 timer a operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tca interval reset functions functions halted halted halted halted halted clock time base reset functions functions functions functions functions halted halted tma reset functions retained retained functions retained retained retained note: when the real-time clock time base function is selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ (s) in the count cycle.
rev. 4.00, 05/03, page 234 of 562 9.2.5 application note when bit 0 (tackstp) of the clock stop register 1 (ckstpr1) is cleared to 0, bit 3 (tma3) of the timer mode register a (tma) cannot be rewritten. set bit 0 (tackstp) of the clock stop register 1 (ckstpr1) to 1 before rewriting bit 3 (tma3) of the timer mode register a (tma). 9.3 timer c 9.3.1 overview timer c is an 8-bit timer that increments or decrements each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer c are given below. ? choice of seven internal clock sources ( /8192, /2048, /512, /64, /16, /4, w /4) or an external clock (can be used to count external events). ? an interrupt is requested when the counter overflows. ? up/down-counter switching is possible by hardware or software. ? subactive mode or subsleep mode operation is possible when w /4 is selected as the internal clock, or when an external clock is selected. ? use of module standby mode enables this module to be placed in standby mode independently when not used.
rev. 4.00, 05/03, page 235 of 562 2. block diagram figure 9.2 shows a block diagram of timer c. ud tmic w /4 pss tmc internal data bus tcc tlc irrtc notation: tmc tcc tlc irrtc pss : timer mode register c : timer counter c : timer load register c : timer c overflow interrupt request flag : prescaler s figure 9.2 block diagram of timer c 3. pin configuration table 9.4 shows the timer c pin configuration. table 9.4 pin configuration name abbr. i/o function timer c event input tmic input input pin for event input to tcc timer c up/down select ud input timer c up/down-count selection
rev. 4.00, 05/03, page 236 of 562 4. register configuration table 9.5 shows the register configuration of timer c. table 9.5 timer c registers name abbr. r/w initial value address timer mode register c tmc r/w h'18 h'ffb4 timer counter c tcc r h'00 h'ffb5 timer load register c tlc w h'00 h'ffb5 clock stop register 1 ckstpr1 r/w h'ff h'fffa 9.3.2 register descriptions 1. timer mode register c (tmc) bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 4 1 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w tmc is an 8-bit read/write register for selecting the auto-reload function and input clock, and performing up/down-counter control. upon reset, tmc is initialized to h'18. bit 7: auto-reload function select (tmc7) bit 7 selects whether timer c is used as an interval timer or auto-reload timer. bit 7 tmc7 description 0 interval timer function selected (initial value) 1 auto-reload function selected
rev. 4.00, 05/03, page 237 of 562 bits 6 and 5: counter up/down control (tmc6, tmc5) selects whether tcc up/down control is performed by hardware using ud pin input, or whether tcc functions as an up-counter or a down-counter. bit 6 tmc6 bit 5 tmc5 description 0 0 tcc is an up-counter (initial value) 0 1 tcc is a down-counter 1 * hardware control by ud pin input ud pin input high: down-counter ud pin input low: up-counter * : don't care bits 4 and 3: reserved bits bits 4 and 3 are reserved; they are always read as 1 and cannot be modified. bits 2 to 0: clock select (tmc2 to tmc0) bits 2 to 0 select the clock input to tcc. for external event counting, either the rising or falling edge can be selected. bit 2 tmc2 bit 1 tmc1 bit 0 tmc0 description 0 0 0 internal clock: /8192 (initial value) 0 0 1 internal clock: /2048 0 1 0 internal clock: /512 0 1 1 internal clock: /64 1 0 0 internal clock: /16 1 0 1 internal clock: /4 1 1 0 internal clock: w /4 1 1 1 external event (tmic): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg1 in the irq edge select register (iegr). see 1. irq edge select register (iegr) in section 3.3.2 for details. irq1 in port mode register b (pmrb) must be set to 1 before setting 111 in bits tmc2 to tmc0.
rev. 4.00, 05/03, page 238 of 562 2. timer counter c (tcc) bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r tcc is an 8-bit read-only up/down-counter, which is incremented or decremented by internal clock or external event input. the clock source for input to this counter is selected by bits tmc2 to tmc0 in timer mode register c (tmc). tcc values can be read by the cpu at any time. when tcc overflows from h'ff to h'00 or to the value set in tlc, or underflows from h'00 to h'ff or to the value set in tlc, the irrtc bit in irr2 is set to 1. tcc is allocated to the same address as tlc. upon reset, tcc is initialized to h'00. 3. timer load register c (tlc) bit initial value read/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w tlc is an 8-bit write-only register for setting the reload value of timer counter c (tcc). when a reload value is set in tlc, the same value is loaded into timer counter c as well, and tcc starts counting up/down from that value. when tcc overflows or underflows during operation in auto-reload mode, the tlc value is loaded into tcc. accordingly, overflow/underflow period can be set within the range of 1 to 256 input clocks. the same address is allocated to tlc as to tcc. upon reset, tlc is initialized to h'00.
rev. 4.00, 05/03, page 239 of 562 4. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer c is described here. for details of the other bits, see the sections on the relevant modules. bit 1: timer c module standby mode control (tcckstp) bit 1 controls setting and clearing of module standby mode for timer c. tcckstp description 0 timer c is set to module standby mode 1 timer c module standby mode is cleared (initial value) 9.3.3 timer operation 1. interval timer operation when bit tmc7 in timer mode register c (tmc) is cleared to 0, timer c functions as an 8-bit interval timer. upon reset, tcc is initialized to h'00 and tmc to h'18, so tcc continues up-counting as an interval up-counter without halting immediately after a reset. the timer c operating clock is selected from seven internal clock signals output by prescalers s and w, or an external clock input at pin tmic. the selection is made by bits tmc2 to tmc0 in tmc. tcc up/down-count control can be performed either by software or hardware. the selection is made by bits tmc6 and tmc5 in tmc. after the count value in tcc reaches h'ff (h'00), the next clock input causes timer c to overflow (underflow), setting bit irrtc in irr2 to 1. if ientc = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested. at overflow (underflow), tcc returns to h'00 (h'ff) and starts counting up (down) again. during interval timer operation (tmc7 = 0), when a value is set in timer load register c (tlc), the same value is set in tcc. note: for details on interrupts, see section 3.3, interrupts.
rev. 4.00, 05/03, page 240 of 562 2. auto-reload timer operation setting bit tmc7 in tmc to 1 causes timer c to function as an 8-bit auto-reload timer. when a reload value is set in tlc, the same value is loaded into tcc, becoming the value from which tcc starts its count. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow/underflow. the tlc value is then loaded into tcc, and the count continues from that value. the overflow/underflow period can be set within a range from 1 to 256 input clocks, depending on the tlc value. the clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmc7 = 1), when a new value is set in tlc, the tlc value is also set in tcc. 3. event counter operation timer c can operate as an event counter, counting rising or falling edges of an external event signal input at pin tmic. external event counting is selected by setting bits tmc2 to tmc0 in timer mode register c (tmc) to all 1s (111). tcc counts up/down at the rising/falling edge of an external event signal input at pin tmic. when timer c is used to count external event input, bit irq1 in pmrb should be set to 1 and bit ien1 in ienr1 cleared to 0 to disable interrupt irq1 requests. 4. tcc up/down control by hardware with timer c, tcc up/down control can be performed by ud pin input. when bit tmc6 in tmc is set to 1, tcc functions as an up-counter when ud pin input is low, and as a down-counter when high. when using ud pin input, set bit ud in pmr3 to 1.
rev. 4.00, 05/03, page 241 of 562 9.3.4 timer c operation states table 9.6 summarizes the timer c operation states. table 9.6 timer c operation states operation mode reset active sleep watch sub- active sub- sleep standby module standby tcc intervalreset functions functions halted functions/ halted * functions/ halted * halted halted auto reload reset functions functions halted functions/ halted * functions/ halted * halted halted tmc reset functions retained retained functions retained retained retained note: * when w/4 is selected as the tcc internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode or subsleep mode, either select w/4 as the internal clock or select an external clock. the counter will not operate on any other internal clock. if w/4 is selected as the internal clock for the counter when w/8 has been selected as subclock sub , the lower 2 bits of the counter operate on the same cycle, and the operation of the least significant bit is unrelated to the operation of the counter.
rev. 4.00, 05/03, page 242 of 562 9.4 timer f 9.4.1 overview timer f is a 16-bit timer with a built-in output compare function. as well as counting external events, timer f also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. timer f can also be used as two independent 8-bit timers (timer fh and timer fl). 1. features features of timer f are given below. ? choice of four internal clock sources ( /32, /16, /4, w/4) or an external clock (can be used as an external event counter) ? tmofh/tmofl pin toggle output provided using a single compare match signal (toggle output initial value can be set) ? counter resetting by a compare match signal ? two interrupt sources: one compare match, one overflow ? can operate as two independent 8-bit timers (timer fh and timer fl) (in 8-bit mode). timer fh 8-bit timer * timer fl 8-bit timer/event counter internal clock choice of 4 ( /32, /16, /4, w/4) event input tmif pin toggle output one compare match signal, output to tmofh pin(initial value settable) one compare match signal, output to tmofl pin (initial value settable) counter reset counter can be reset by compare match signal interrupt sources one compare match one overflow note: * when timer f operates as a 16-bit timer, it operates on the timer fl overflow signal. ? operation in watch mode, subactive mode, and subsleep mode when w/4 is selected as the internal clock, timer f can operate in watch mode, subactive mode, and subsleep mode. ? use of module standby mode enables this module to be placed in standby mode independently when not used.
rev. 4.00, 05/03, page 243 of 562 2. block diagram figure 9.3 shows a block diagram of timer f. pss toggle circuit toggle circuit tmif w /4 tmofl tmofh tcrf tcfl ocrfl tcfh ocrfh tcsrf comparator comparator match irrtfh irrtfl notation: tcrf: tcsrf: tcfh: tcfl: ocrfh: ocrfl: irrtfh: irrtfl: pss: timer control register f timer control/status register f 8-bit timer counter fh 8-bit timer counter fl output compare register fh output compare register fl timer fh interrupt request flag timer fl interrupt request flag prescaler s internal data bus figure 9.3 block diagram of timer f
rev. 4.00, 05/03, page 244 of 562 3. pin configuration table 9.7 shows the timer f pin configuration. table 9.7 pin configuration name abbr. i/o function timer f event input tmif input event input pin for input to tcfl timer fh output tmofh output timer fh toggle output pin timer fl output tmofl output timer fl toggle output pin 4. register configuration table 9.8 shows the register configuration of timer f. table 9.8 timer f registers name abbr. r/w initial value address timer control register f tcrf w h'00 h'ffb6 timer control/status register f tcsrf r/w h'00 h'ffb7 8-bit timer counter fh tcfh r/w h'00 h'ffb8 8-bit timer counter fl tcfl r/w h'00 h'ffb9 output compare register fh ocrfh r/w h'ff h'ffba output compare register fl ocrfl r/w h'ff h'ffbb clock stop register 1 ckstpr1 r/w h'ff h'fffa
rev. 4.00, 05/03, page 245 of 562 9.4.2 register descriptions 1. 16-bit timer counter (tcf) 8-bit timer counter (tcfh) 8-bit timer counter (tcfl) 15 14 13 12 11 10 9 8 tcf tcfh tcfl 76543210 0000000000000000 r/w bit: initial value: read/write: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcf is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters tcfh and tcfl. in addition to the use of tcf as a 16-bit counter with tcfh as the upper 8 bits and tcfl as the lower 8 bits, tcfh and tcfl can also be used as independent 8-bit counters. tcfh and tcfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see section 9.4.3, cpu interface. tcfh and tcfl are each initialized to h'00 upon reset. a. 16-bit mode (tcf) when cksh2 is cleared to 0 in tcrf, tcf operates as a 16-bit counter. the tcf input clock is selected by bits cksl2 to cksl0 in tcrf. tcf can be cleared in the event of a compare match by means of cclrh in tcsrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf is 1 at this time, irrtfh is set to 1 in irr2, and if ientfh in ienr2 is 1, an interrupt request is sent to the cpu. b. 8-bit mode (tcfl/tcfh) when cksh2 is set to 1 in tcrf, tcfh, and tcfl operate as two independent 8-bit counters. the tcfh (tcfl) input clock is selected by bits cksh2 to cksh0 (cksl2 to cksl0) in tcrf. tcfh (tcfl) can be cleared in the event of a compare match by means of cclrh (cclrl) in tcsrf. when tcfh (tcfl) overflows from h'ff to h'00, ovfh (ovfl) is set to 1 in tcsrf. if ovieh (oviel) in tcsrf is 1 at this time, irrtfh (irrtfl) is set to 1 in irr2, and if ientfh (ientfl) in ienr2 is 1, an interrupt request is sent to the cpu.
rev. 4.00, 05/03, page 246 of 562 2. 16-bit output compare register (ocrf) 8-bit output compare register (ocrfh) 8-bit output compare register (ocrfl) 15 14 13 12 11 10 9 8 ocrf ocrfh ocrfl 76543210 1111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ocrf is a 16-bit read/write register composed of the two registers ocrfh and ocrfl. in addition to the use of ocrf as a 16-bit register with ocrfh as the upper 8 bits and ocrfl as the lower 8 bits, ocrfh and ocrfl can also be used as independent 8-bit registers. ocrfh and ocrfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see section 9.4.3, cpu interface. ocrfh and ocrfl are each initialized to h'ff upon reset. a. 16-bit mode (ocrf) when cksh2 is cleared to 0 in tcrf, ocrf operates as a 16-bit register. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. at the same time, irrtfh is set to 1 in irr2. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin by means of compare matches, and the output level can be set (high or low) by means of tolh in tcrf. b. 8-bit mode (ocrfh/ocrfl) when cksh2 is set to 1 in tcrf, ocrfh, and ocrfl operate as two independent 8-bit registers. ocrfh contents are compared with tcfh, and ocrfl contents are with tcfl. when the ocrfh (ocrfl) and tcfh (tcfl) values match, cmfh (cmfl) is set to 1 in tcsrf. at the same time, irrtfh (irrtfl) is set to 1 in irr2. if ientfh (ientfl) in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin (tmofl pin) by means of compare matches, and the output level can be set (high or low) by means of tolh (toll) in tcrf.
rev. 4.00, 05/03, page 247 of 562 3. timer control register f (tcrf) tolh cksl2 cksl1 cksl0 cksh2 cksh1 cksh0 toll 76543210 0 0000000 w www www w bit: initial value: read/write: tcrf is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the tmofh and tmofl pins. tcrf is initialized to h'00 upon reset. bit 7: toggle output level h (tolh) bit 7 sets the tmofh pin output level. the output level is effective immediately after this bit is written. bit 7 tolh description 0 low level (initial value) 1 high level bits 6 to 4: clock select h (cksh2 to cksh0) bits 6 to 4 select the clock input to tcfh from among four internal clock sources or tcfl overflow. bit 6 cksh2 bit 5 cksh1 bit 4 cksh0 description 0 0 0 16-bit mode, counting on tcfl overflow signal (initial value) 001 010 011use prohibited 100internal clock: counting on /32 101internal clock: counting on /16 110internal clock: counting on /4 111internal clock: counting on w/4
rev. 4.00, 05/03, page 248 of 562 bit 3: toggle output level l (toll) bit 3 sets the tmofl pin output level. the output level is effective immediately after this bit is written. bit 3 toll description 0 low level (initial value) 1 high level bits 2 to 0: clock select l (cksl2 to cksl0) bits 2 to 0 select the clock input to tcfl from among four internal clock sources or external event input. bit 2 cksl2 bit 1 cksl1 bit 0 cksl0 description 000 001 counting on external event (tmif) rising/falling edge * (initial value) 010 011use prohibited 100internal clock: counting on /32 101internal clock: counting on /16 110internal clock: counting on /4 111internal clock: counting on w/4 note: * external event edge selection is set by ieg3 in the irq edge select register (iegr). for details, see 1. irq edge select register (iegr) in section 3.3.2. note that the timer f counter may increment if the setting of irq3 in port mode register 1 (pmr1) is changed from 0 to 1 while the tmif pin is low in order to change the tmif pin function.
rev. 4.00, 05/03, page 249 of 562 4. timer control/status register f (tcsrf) ovfh cmfl oviel cclrl cmfh ovieh cclrh ovfl 76543210 0 0000000 r/(w) * r/(w) * r/w r/w r/(w) * r/w r/w r/(w) * note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. bit: initial value: read/write: tcsrf is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. tcsrf is initialized to h'00 upon reset. bit 7: timer overflow flag h (ovfh) bit 7 is a status flag indicating that tcfh has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 ovfh description 0 clearing condition: (initial value) after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting condition: set when tcfh overflows from hff to h00 bit 6: compare match flag h (cmfh) bit 6 is a status flag indicating that tcfh has matched ocrfh. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 cmfh description 0 clearing condition: (initial value) after reading cmfh = 1, cleared by writing 0 to cmfh 1 setting condition: set when the tcfh value matches the ocrfh value
rev. 4.00, 05/03, page 250 of 562 bit 5: timer overflow interrupt enable h (ovieh) bit 5 selects enabling or disabling of interrupt generation when tcfh overflows. bit 5 ovieh description 0 tcfh overflow interrupt request is disabled (initial value) 1 tcfh overflow interrupt request is enabled bit 4: counter clear h (cclrh) in 16-bit mode, bit 4 selects whether tcf is cleared when tcf and ocrf match. in 8-bit mode, bit 4 selects whether tcfh is cleared when tcfh and ocrfh match. bit 4 cclrh description 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled (initial value) 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled bit 3: timer overflow flag l (ovfl) bit 3 is a status flag indicating that tcfl has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 3 ovfl description 0 clearing condition: (initial value) after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting condition: set when tcfl overflows from hff to h00
rev. 4.00, 05/03, page 251 of 562 bit 2: compare match flag l (cmfl) bit 2 is a status flag indicating that tcfl has matched ocrfl. this flag is set by hardware and cleared by software. it cannot be set by software. bit 2 cmfl description 0 clearing condition: (initial value) after reading cmfl = 1, cleared by writing 0 to cmfl 1 setting condition: set when the tcfl value matches the ocrfl value bit 1: timer overflow interrupt enable l (oviel) bit 1 selects enabling or disabling of interrupt generation when tcfl overflows. bit 1 oviel description 0 tcfl overflow interrupt request is disabled (initial value) 1 tcfl overflow interrupt request is enabled bit 0: counter clear l (cclrl) bit 0 selects whether tcfl is cleared when tcfl and ocrfl match. bit 0 cclrl description 0 tcfl clearing by compare match is disabled (initial value) 1 tcfl clearing by compare match is enabled
rev. 4.00, 05/03, page 252 of 562 5. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer f is described here. for details of the other bits, see the sections on the relevant modules. bit 2: timer f module standby mode control (tfckstp) bit 2 controls setting and clearing of module standby mode for timer f. tfckstp description 0 timer f is set to module standby mode 1 timer f module standby mode is cleared (initial value) 9.4.3 cpu interface tcf and ocrf are 16-bit read/write registers, but the cpu is connected to the on-chip peripheral modules by an 8-bit data bus. when the cpu accesses these registers, it therefore uses an 8-bit temporary register (temp). in 16-bit mode, tcf read/write access and ocrf write access must be performed 16 bits at a time (using two consecutive byte-size mov instructions), and the upper byte must be accessed before the lower byte. data will not be transferred correctly if only the upper byte or only the lower byte is accessed. in 8-bit mode, there are no restrictions on the order of access. 1. write access write access to the upper byte results in transfer of the upper-byte write data to temp. next, write access to the lower byte results in transfer of the data in temp to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte.
rev. 4.00, 05/03, page 253 of 562 figure 9.4 shows an example in which h'aa55 is written to tcf. write to upper byte cpu (haa) temp (haa) tcfh ( ) tcfl ( ) bus interface module data bus write to lower byte cpu (h55) temp (haa) tcfh (haa) tcfl (h55) bus interface module data bus figure 9.4 write access to tcf (cpu tcf)
rev. 4.00, 05/03, page 254 of 562 2. read access in access to tcf, when the upper byte is read the upper-byte data is transferred directly to the cpu and the lower-byte data is transferred to temp. next, when the lower byte is read, the lower-byte data in temp is transferred to the cpu. in access to ocrf, when the upper byte is read the upper-byte data is transferred directly to the cpu. when the lower byte is read, the lower-byte data is transferred directly to the cpu. figure 9.5 shows an example in which tcf is read when it contains h'aaff. read upper byte cpu (haa) temp (hff) tcfh (haa) tcfl (hff) bus interface module data bus read lower byte cpu (hff) temp (hff) tcfh (ab) * tcfl (00) * bus interface module data bus note: * hab00 if counter has been updated once. figure 9.5 read access to tcf (tcf cpu)
rev. 4.00, 05/03, page 255 of 562 9.4.4 operation timer f is a 16-bit counter that increments on each input clock pulse. the timer f value is constantly compared with the value set in output compare register f, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. timer f can also function as two independent 8-bit timers. 1. timer f operation timer f has two operating modes, 16-bit timer mode and 8-bit timer mode. the operation in each of these modes is described below. a. operation in 16-bit timer mode when cksh2 is cleared to 0 in timer control register f (tcrf), timer f operates as a 16-bit timer. following a reset, timer counter f (tcf) is initialized to h'0000, output compare register f (ocrf) to h'ffff, and timer control register f (tcrf) and timer control/status register f (tcsrf) to h'00. the counter starts incrementing on external event (tmif) input. the external event edge selection is set by ieg3 in the irq edge select register (iegr). the timer f operating clock can be selected from three internal clocks output by prescaler s or an external clock by means of bits cksl2 to cksl0 in tcrf. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu, and at the same time, tmofh pin output is toggled. if cclrh in tcsrf is 1, tcf is cleared. tmofh pin output can also be set by tolh in tcrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf and ientfh in ienr2 are both 1, an interrupt request is sent to the cpu. b. operation in 8-bit timer mode when cksh2 is set to 1 in tcrf, tcf operates as two independent 8-bit timers, tcfh and tcfl. the tcfh/tcfl input clock is selected by cksh2 to cksh0/cksl2 to cksl0 in tcrf. when the ocrfh/ocrfl and tcfh/tcfl values match, cmfh/cmfl is set to 1 in tcsrf. if ientfh/ientfl in ienr2 is 1, an interrupt request is sent to the cpu, and at the same time, tmofh pin/tmofl pin output is toggled. if cclrh/cclrl in tcsrf is 1, tcfh/tcfl is cleared. tmofh pin/tmofl pin output can also be set by tolh/toll in tcrf. when tcfh/tcfl overflows from h'ff to h'00, ovfh/ovfl is set to 1 in tcsrf. if ovieh/oviel in tcsrf and ientfh/ientfl in ienr2 are both 1, an interrupt request is sent to the cpu.
rev. 4.00, 05/03, page 256 of 562 2. tcf increment timing tcf is incremented by clock input (internal clock or external event input). a. internal clock operation bits cksh2 to cksh0 or cksl2 to cksl0 in tcrf select one of four internal clock sources ( /32, /16, /4, or w/4) created by dividing the system clock ( or w). b. external event operation external event input is selected by clearing cksl2 to 0 in tcrf. tcf can increment on either the rising or falling edge of external event input. external event edge selection is set by ieg3 in the interrupt controllers iegr register. an external event pulse width of at least 2 system clocks ( ) is necessary. shorter pulses will not be counted correctly. 3. tmofh/tmofl output timing in tmofh/tmofl output, the value set in tolh/toll in tcrf is output. the output is toggled by the occurrence of a compare match. figure 9.6 shows the output timing. tmif (when ieg3 = 1) count input clock tcf ocrf tmofh tmofl compare match signal nn n n n+1 n+1 figure 9.6 tmofh/tmofl output timing
rev. 4.00, 05/03, page 257 of 562 4. tcf clear timing tcf can be cleared by a compare match with ocrf. 5. timer overflow flag (ovf) set timing ovf is set to 1 when tcf overflows from h'ffff to h'0000. 6. compare match flag set timing the compare match flag (cmfh or cmfl) is set to 1 when the tcf and ocrf values match. the compare match signal is generated in the last state during which the values match (when tcf is updated from the matching value to a new value). when tcf matches ocrf, the compare match signal is not generated until the next counter clock. 7. timer f operation modes timer f operation modes are shown in table 9.9. table 9.9 timer f operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby tcf reset functions functions functions/ halted * functions/ halted * functions/ halted * halted halted ocrf reset functions held held functions held held held tcrf reset functions held held functions held held held tcsrf reset functions held held functions held held held note: * when w /4 is selected as the tcf internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode, watch mode, or subsleep mode, w /4 must be selected as the internal clock. the counter will not operate if any other internal clock is selected.
rev. 4.00, 05/03, page 258 of 562 9.4.5 application notes the following types of contention and operation can occur when timer f is used. 1. 16-bit timer mode in toggle output, tmofh pin output is toggled when all 16 bits match and a compare match signal is generated. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. tmofl pin output is unstable in 16-bit mode, and should not be used; the tmofl pin should be used as a port pin. if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. compare match flag cmfh is set when all 16 bits match and a compare match signal is generated. compare match flag cmfl is set if the setting conditions for the lower 8 bits are satisfied. when tcf overflows, ovfh is set. ovfl is set if the setting conditions are satisfied when the lower 8 bits overflow. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 2. 8-bit timer mode a. tcfh, ocrfh in toggle output, tmofh pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. if an ocrfh write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfh clock. if a tcfh write and overflow signal output occur simultaneously, the overflow signal is not output. b. tcfl, ocrfl in toggle output, tmofl pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, toll data is output to the tmofl pin as a result of the tcrf write.
rev. 4.00, 05/03, page 259 of 562 if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. 3. clear timer fh, timer fl interrupt request flags (irrtfh, irrtfl), timer overflow flags h, l (ovfh, ovfl) and compare match flags h, l (cmfh, cmfl) when w/4 is selected as the internal clock, interrupt factor generation signal will be operated with w and the signal will be outputted with w width. and, overflow signal and compare match signal are controlled with 2 cycles of w signals. those signals are outputted with 2 cycles width of w (figure 9.7) in active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of interrupt factor generation signal, same interrupt request flag is set. (figure 9.7 (1)) and, you cannot be cleared timer overflow flag and compare match flag during the term of validity of overflow signal and compare match signal. for interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer fh, timer fl interrupt might be repeated. (figure 9.7 (2)) therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. and, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register f (tcsrf) after the time that calculated with below (1) formula. for st of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of rte instruction when mulxu, divxu instruction is not used, 14 states when mulxu, divxu instruction is used) in subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. the term of validity of interrupt factor generation signal = 1 cycle of w + waiting time for completion of executing instruction + interrupt time synchronized with = 1/ w + st (1/ ) + (2/ ) (second).....(1) st: executing number of execution states method 1 is recommended to operate for time efficiency. method 1 1. prohibit interrupt in interrupt handling routine (set ienfh, ienfl to 0).
rev. 4.00, 05/03, page 260 of 562 2. after program process returned normal handling, clear interrupt request flags (irrtfh, irrtfl) after more than that calculated with (1) formula. 3. after read timer control status register f (tcsrf), clear timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). 4. operate interrupt permission (set ienfh, ienfl to 1). method 2 1. set interrupt handling routine time to more than time that calculated with (1) formula. 2. clear interrupt request flags (irrtfh, irrtfl) at the end of interrupt handling routine. 3. after read timer control status register f (tcsrf), clear timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). all above attentions are also applied in 16-bit mode and 8-bit mode. program process w interrupt request flag (irrtfh, irrtfl) interrupt factor generation signal (internal signal, nega-active) overflow signal, compare match signal (internal signal, nega-active) interrupt interrupt normal interrupt request flag clear interrupt request flag clear (1) (2) figure 9.7 clear interrupt request flag when interrupt factor generation signal is valid 4. timer counter (tcf) read/write when w/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on tcf is impossible. and, when read tcf, as the system clock and internal clock are mutually asynchronous, tcf synchronizes with synchronization circuit. this results in a maximum tcf read value error of 1. when read/write tcf in active (high-speed, medium-speed) mode is needed, please select internal clock except for w/4 before read/write. in subactive mode, even w/4 is selected as the internal clock, normal read/write tcf is possible.
rev. 4.00, 05/03, page 261 of 562 9.5 timer g 9.5.1 overview timer g is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). high-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle. if input capture input is not set, timer g functions as an 8-bit interval timer. 1. features features of timer g are given below. ? choice of four internal clock sources ( /64, /32, /2, w/4) ? dedicated input capture functions for rising and falling edges ? level detection at counter overflow ? it is possible to detect whether overflow occurred when the input capture input signal was high or when it was low. ? selection of whether or not the counter value is to be cleared at the input capture input signal rising edge, falling edge, or both edges ? two interrupt sources: one input capture, one overflow. the input capture input signal rising or falling edge can be selected as the interrupt source. ? a built-in noise canceler eliminates high-frequency component noise in the input capture input signal. ? watch mode, subactive mode, or subsleep mode operation is possible when w/4 is selected as the internal clock. ? use of module standby mode enables this module to be placed in standby mode independently when not used.
rev. 4.00, 05/03, page 262 of 562 2. block diagram figure 9.8 shows a block diagram of timer g. pss tmg icrgf tcg icrgr noise canceler edge detector level detector irrtg w /4 tmig ncs notation: tmg tcg icrgf icrgr irrtg ncs pss : timer mode register g : timer counter g : input capture register gf : input capture register gr : timer g interrupt request flag : noise canceler select : prescaler s internal data bus figure 9.8 block diagram of timer g
rev. 4.00, 05/03, page 263 of 562 3. pin configuration table 9.10 shows the timer g pin configuration. table 9.10 pin configuration name abbr. i/o function input capture input tmig input input capture input pin 4. register configuration table 9.11 shows the register configuration of timer g. table 9.11 timer g registers name abbr. r/w initial value address timer control register g tmg r/w h'00 h'ffbc timer counter g tcg h'00 input capture register gf icrgf r h'00 h'ffbd input capture register gr icrgr r h'00 h'ffbe clock stop register 1 ckstpr1 r/w h'ff h'fffa 9.5.2 register descriptions 1. timer counter g (tcg) tcg7 tcg2 tcg1 tcg0 tcg6 tcg5 tcg4 tcg3 76543210 0 0000000 bit: initial value: read/write: tcg is an 8-bit up-counter which is incremented by clock input. the input clock is selected by bits cks1 and cks0 in tmg. tmig in pmr1 is set to 1 to operate tcg as an input capture timer, or cleared to 0 to operate tcg as an interval timer * . in input capture timer operation, the tcg value can be cleared by the rising edge, falling edge, or both edges of the input capture input signal, according to the setting made in tmg. when tcg overflows from h'ff to h'00, if ovie in tmg is 1, irrtg in irr2 is set to 1, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts.
rev. 4.00, 05/03, page 264 of 562 tcg cannot be read or written by the cpu. it is initialized to h'00 upon reset. note: * an input capture signal may be generated when tmig is modified. 2. input capture register gf (icrgf) icrgf7 icrgf2 icrgf1 icrgf0 icrgf6 icrgf5 icrgf4 icrgf3 76543210 0 0000000 r rrr rrr r bit: initial value: read/write: icrgf is an 8-bit read-only register. when a falling edge of the input capture input signal is detected, the current tcg value is transferred to icrgf. if iiegs in tmg is 1 at this time, irrtg in irr2 is set to 1, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts. to ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2 sub (when the noise canceler is not used). icrgf is initialized to h'00 upon reset. 3. input capture register gr (icrgr) icrgr7 icrgr2 icrgr1 icrgr0 icrgr6 icrgr5 icrgr4 icrgr3 76543210 0 0000000 r rrr rrr r bit: initial value: read/write: icrgr is an 8-bit read-only register. when a rising edge of the input capture input signal is detected, the current tcg value is transferred to icrgr. if iiegs in tmg is 0 at this time, irrtg in irr2 is set to 1, and if ientg in ienr2 is 1, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts. to ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2 sub (when the noise canceler is not used). icrgr is initialized to h'00 upon reset.
rev. 4.00, 05/03, page 265 of 562 4. timer mode register g (tmg) ovfh cclr0 cks1 cks0 ovfl ovie iiegs cclr1 76543210 0 0000000 r/(w) * r/w r/w r/w r/(w) * r/w r/w r/w bit: initial value: read/write: note: * bits 7 and 6 can only be written with 0, for flag clearing. tmg is an 8-bit read/write register that performs tcg clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags. tmg is initialized to h'00 upon reset. bit 7: timer overflow flag h (ovfh) bit 7 is a status flag indicating that tcg has overflowed from h'ff to h'00 when the input capture input signal is high. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 ovfh description 0 clearing condition: after reading ovfh = 1, cleared by writing 0 to ovfh (initial value) 1 setting condition: set when tcg overflows from h'ff to h'00 bit 6: timer overflow flag l (ovfl) bit 6 is a status flag indicating that tcg has overflowed from h'ff to h'00 when the input capture input signal is low, or in interval operation. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 ovfl description 0 clearing condition: after reading ovfl = 1, cleared by writing 0 to ovfl (initial value) 1 setting condition: set when tcg overflows from h'ff to h'00
rev. 4.00, 05/03, page 266 of 562 bit 5: timer overflow interrupt enable (ovie) bit 5 selects enabling or disabling of interrupt generation when tcg overflows. bit 5 ovie description 0 tcg overflow interrupt request is disabled (initial value) 1 tcg overflow interrupt request is enabled bit 4: input capture interrupt edge select (iiegs) bit 4 selects the input capture input signal edge that generates an interrupt request. bit 4 iiegs description 0 interrupt generated on rising edge of input capture input signal(initial value) 1 interrupt generated on falling edge of input capture input signal bits 3 and 2: counter clear 1 and 0 (cclr1, cclr0) bits 3 and 2 specify whether or not tcg is cleared by the rising edge, falling edge, or both edges of the input capture input signal. bit 3 cclr1 bit 2 cclr0 description 0 0 tcg clearing is disabled (initial value) 0 1 tcg cleared by falling edge of input capture input signal 1 0 tcg cleared by rising edge of input capture input signal 1 1 tcg cleared by both edges of input capture input signal bits 1 and 0: clock select (cks1, cks0) bits 1 and 0 select the clock input to tcg from among four internal clock sources. bit 1 cks1 bit 0 cks0 description 0 0 internal clock: counting on /64 (initial value) 0 1 internal clock: counting on /32 1 0 internal clock: counting on /2 1 1 internal clock: counting on w/4
rev. 4.00, 05/03, page 267 of 562 5. clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w bit: initial value: read/write: ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to timer g is described here. for details of the other bits, see the sections on the relevant modules. bit 3: timer g module standby mode control (tgckstp) bit 3 controls setting and clearing of module standby mode for timer g. tgckstp description 0 timer g is set to module standby mode 1 timer g module standby mode is cleared (initial value)
rev. 4.00, 05/03, page 268 of 562 9.5.3 noise canceler the noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. the noise canceler is set by ncs * in pmr2. figure 9.9 shows a block diagram of the noise canceler. c dq latch c dq latch c dq latch c dq latch c dq latch match detector noise canceler output sampling clock input capture input signal sampling clock t t: set by cks1 and cks0 figure 9.9 noise canceler block diagram the noise canceler consists of five latch circuits connected in series and a match detector circuit. when the noise cancellation function is not used (ncs = 0), the system clock is selected as the sampling clock. when the noise cancellation function is used (ncs = 1), the sampling clock is the internal clock selected by cks1 and cks0 in tmg, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match. if all the outputs do not match, the previous value is retained. after a reset, the noise canceler output is initialized when the falling edge of the input capture input signal has been sampled five times. therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. even if noise cancellation is not used, an input capture input signal pulse width of at least 2 or 2 sub is necessary to ensure that input capture operations are performed properly note: * an input capture signal may be generated when the ncs bit is modified. figure 9.10 shows an example of noise canceler timing. in this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise.
rev. 4.00, 05/03, page 269 of 562 input capture input signal sampling clock noise canceler output eliminated as noise figure 9.10 noise canceler timing (example)
rev. 4.00, 05/03, page 270 of 562 9.5.4 operation timer g is an 8-bit timer with built-in input capture and interval functions. 1. timer g functions timer g is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. the operation of these two functions is described below. a. input capture timer operation when the tmig bit in port mode register 1 (pmr1) is set to 1, timer g functions as an input capture timer * . in a reset, timer mode register g (tmg), timer counter g (tcg), input capture register gf (icrgf), and input capture register gr (icrgr) are all initialized to h'00. following a reset, tcg starts counting on the /64 internal clock. the input clock can be selected from four internal clock sources by bits cks1 and cks0 in tmg. when a rising edge/falling edge is detected in the input capture signal input from the tmig pin, the tcg value at that time is transferred to icrgr/icrgf. when the edge selected by iiegs in tmg is input, irrtg in irr2 is set to 1, and if the ientg bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. for details of the interrupt, see section 3.3, interrupts. tcg can be cleared by a rising edge, falling edge, or both edges of the input capture signal, according to the setting of bits cclr1 and cclr0 in tmg. if tcg overflows when the input capture signal is high, the ovfh bit in tmg is set; if tcg overflows when the input capture signal is low, the ovfl bit in tmg is set. if the ovie bit in tmg is 1 when these bits are set, irrtg in irr2 is set to 1, and if the ientg bit in ienr2 is 1, timer g sends an interrupt request to the cpu. for details of the interrupt, see section 3.3, interrupts. timer g has a built-in noise canceler that enables high-frequency component noise to be eliminated from pulses input from the tmig pin. for details, see section 9.5.3, noise canceler. note: * an input capture signal may be generated when tmig is modified. b. interval timer operation when the tmig bit in pmr1 is cleared to 0, timer g functions as an interval timer. following a reset, tcg starts counting on the /64 internal clock. the input clock can be selected from four internal clock sources by bits cks1 and cks0 in tmg. tcg increments on the selected clock, and when it overflows from h'ff to h'00, the ovfl bit in tmg is set to 1. if the ovie bit in tmg is 1 at this time, irrtg in irr2 is set to 1, and if the ientg bit
rev. 4.00, 05/03, page 271 of 562 in ienr2 is 1, timer g sends an interrupt request to the cpu. for details of the interrupt, see section 3.3, interrupts. 2. count timing tcg is incremented by internal clock input. bits cks1 and cks0 in tmg select one of four internal clock sources ( /64, /32, /2, or w/4) created by dividing the system clock ( ) or watch clock ( w). 3. input capture input timing a. without noise cancellation function for input capture input, dedicated input capture functions are provided for rising and falling edges. figure 9.11 shows the timing for rising/falling edge input capture input. input capture input signal input capture signal f input capture signal r figure 9.11 input capture input timing (without noise cancellation function) b. with noise cancellation function when noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceler results in a delay of five sampling clock cycles from the input capture input signal edge.
rev. 4.00, 05/03, page 272 of 562 figure 9.12 shows the timing in this case. input capture input signal sampling clock noise canceler output input capture signal r figure 9.12 input capture input timing (with noise cancellation function) 4. timing of input capture by input capture input figure 9.13 shows the timing of input capture by input capture input input capture signal tcg n-1 n n hxx n+1 input capture register figure 9.13 timing of input capture by input capture input
rev. 4.00, 05/03, page 273 of 562 5. tcg clear timing tcg can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. figure 9.14 shows the timing for clearing by both edges. input capture input signal input capture signal f input capture signal r tcg n n h00 h00 figure 9.14 tcg clear timing
rev. 4.00, 05/03, page 274 of 562 6. timer g operation modes timer g operation modes are shown in table 9.12. table 9.12 timer g operation modes operation mode reset active sleep watch subactive subsleep standby module standby tcg input capture reset functions * functions * functions/ halted * functions/ halted * functions/ halted * halted halted intervalreset functions * functions * functions/ halted * functions/ halted * functions/ halted * halted halted icrgf reset functions * functions * functions/ halted * functions/ halted * functions/ halted * retained retained icrgr reset functions * functions * functions/ halted * functions/ halted * functions/ halted * retained retained tmg reset functions retained retained functions retained retained retained note: * when w/4 is selected as the tcg internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when w/4 is selected as the tcg internal clock in watch mode, tcg and the noise canceler operate on the w/4 internal clock without regard to the sub subclock ( w/8, w/4, w/2). note that when another internal clock is selected, tcg and the noise canceler do not operate, and input of the input capture input signal does not result in input capture. to operate the timer g in subactive mode or subsleep mode, select w/4 as the tcg internal clock and w/2 as the subclock sub . note that when other internal clock is selected, or when w/8 or w/4 is selected as the subclock sub , tcg and the noise canceler do not operate. 9.5.5 application notes 1. internal clock switching and tcg operation depending on the timing, tcg may be incremented by a switch between different internal clock sources. table 9.13 shows the relation between internal clock switchover timing (by write to bits cks1 and cks0) and tcg operation. when tcg is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock ( ) or subclock ( w). for this reason, in a case like no. 3 in table 9.13 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing tcg to increment.
rev. 4.00, 05/03, page 275 of 562 table 9.13 internal clock switching and tcg operation no. clock levels before and after modifying bits cks1 and cks0 tcg operation 1 goes from low level to low level clock before switching clock after switching count clock tcg n n+1 write to cks1 and cks0 2 goes from low level to high level clock before switching clock after switching count clock tcg n n+1 n+2 write to cks1 and cks0 3 goes from high level to low level * tcg n n+1 n+2 clock before switching clock after switching count clock write to cks1 and cks0
rev. 4.00, 05/03, page 276 of 562 no. clock levels before and after modifying bits cks1 and cks0 tcg operation 4 goes from high level to high level tcg n n+1 n+2 clock before switching clock after switching count clock write to cks1 and cks0 note: * the switchover is seen as a falling edge, and tcg is incremented. 2. notes on port mode register modification the following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function. ? switching input capture input pin function note that when the pin function is switched by modifying tmig in port mode register 1 (pmr1), which performs input capture input pin control, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.14. table 9.14 input capture input signal input edges due to input capture input pin switching, and conditions for their occurrence input capture input signal input edge conditions generation of rising edge when tmig is modified from 0 to 1 while the tmig pin is high when ncs is modified from 0 to 1 while the tmig pin is high, then tmig is modified from 0 to 1 before the signal is sampled five times by the noise canceler generation of falling edge when tmig is modified from 1 to 0 while the tmig pin is high when ncs is modified from 0 to 1 while the tmig pin is low, then tmig is modified from 0 to 1 before the signal is sampled five times by the noise canceler when ncs is modified from 0 to 1 while the tmig pin is high, then tmig is modified from 1 to 0 after the signal is sampled five times by the noise canceler note: when the p1 3 pin is not set as an input capture input pin, the timer g input capture input signal is low.
rev. 4.00, 05/03, page 277 of 562 ? switching input capture input noise canceler function when performing noise canceler function switching by modifying ncs in port mode register 2 (pmr2), which controls the input capture input noise canceler, tmig should first be cleared to 0. note that if ncs is modified without first clearing tmig, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. input capture input signal input edges, and the conditions for their occurrence, are summarized in table 9.15. table 9.15 input capture input signal input edges due to noise canceler function switching, and conditions for their occurrence input capture input signal input edge conditions generation of rising edge when the tmig pin is modified from 0 to 1 while tmig is 1, then ncs is modified from 0 to 1 before the signal is sampled five times by the noise canceler generation of falling edge when the tmig pin is modified from 1 to 0 while tmig is 1, then ncs is modified from 1 to 0 before the signal is sampled five times by the noise canceler
rev. 4.00, 05/03, page 278 of 562 when the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (iiegs) bit, the interrupt request flag will be set to 1. the interrupt request flag should therefore be cleared to 0 before use. figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag clearing. when switching the pin function, set the interrupt-disabled state before manipulating the port mode register, then, after the port mode register operation has been performed, wait for the time required to confirm the input capture input signal as an input capture signal (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), before clearing the interrupt enable flag to 0. there are two ways of preventing interrupt request flag setting when the pin function is switched: by controlling the pin level so that the conditions shown in tables 9.14 and 9.15 are not satisfied, or by setting the opposite of the generated edge in the iiegs bit in tmg. set i bit in ccr to 1 manipulate port mode register * tmig confirmation time clear interrupt request flag to 0 clear i bit in ccr to 0 disable interrupts. (interrupts can also be disabled by manipulating the interrupt enable bit in interrupt enable register 2.) after manipulating the port mode register, wait for the tmig confirmation time * (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), then clear the interrupt enable flag to 0. enable interrupts figure 9.15 port mode register manipulation and interrupt enable flag clearing procedure
rev. 4.00, 05/03, page 279 of 562 9.5.6 timer g application example using timer g, it is possible to measure the high and low widths of the input capture input signal as absolute values. for this purpose, cclr1 and cclr0 in tmg should both be set to 1. figure 9.16 shows an example of the operation in this case. counter cleared tcg hff h00 input capture input signal input capture register gf input capture register gr figure 9.16 timer g application example
rev. 4.00, 05/03, page 280 of 562 9.6 watchdog timer 9.6.1 overview the watchdog timer has an 8-bit counter that is incremented by an input clock. if a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. features features of the watchdog timer are given below. ? incremented by internal clock source ( /8192 or w/32). ? a reset signal is generated when the counter overflows. the overflow period can be set from from 1 to 256 times 8192/ or 32/ w (from approximately 4 ms to 1000 ms when = 2.00 mhz). ? use of module standby mode enables this module to be placed in standby mode independently when not used. 2. block diagram figure 9.17 shows a block diagram of the watchdog timer. pss tcsrw tcw /8192 notation: tcsrw: tcw: pss: w /32 internal data bus reset signal timer control/status register w timer counter w prescaler s figure 9.17 block diagram of watchdog timer
rev. 4.00, 05/03, page 281 of 562 3. register configuration table 9.16 shows the register configuration of the watchdog timer. table 9.16 watchdog timer registers name abbr. r/w initial value address timer control/status register w tcsrw r/w h'aa h'ffb2 timer counter w tcw r/w h'00 h'ffb3 clock stop register 2 ckstpr2 r/w h'ff h'fffb port mode register 2 pmr2 r/w h'd8 h'ffc9 9.6.2 register descriptions 1. timer control/status register w (tcsrw) bit initial value read/write 7 b6wi 1 r 6 tcwe 0 (r/w) * 5 b4wi 1 r 4 tcsrwe 0 (r/w) * 3 b2wi 1 r 0 wrst 0 (r/w) * 2 wdon 0 (r/w) * 1 b0wi 1 r note: * write is enabled only under certain conditions, which are given in the descriptions of the individual bits. tcsrw is an 8-bit read/write register that controls write access to tcw and tcsrw itself, controls watchdog timer operations, and indicates operating status. bit 7: bit 6 write disable (b6wi) bit 7 controls the writing of data to bit 6 in tcsrw. bit 7 b6wi description 0 bit 6 is write-enabled 1 bit 6 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored.
rev. 4.00, 05/03, page 282 of 562 bit 6: timer counter w write enable (tcwe) bit 6 controls the writing of data to tcw. bit 6 tcwe description 0 data cannot be written to tcw (initial value) 1 data can be written to tcw bit 5: bit 4 write disable (b4wi) bit 5 controls the writing of data to bit 4 in tcsrw. bit 5 b4wi description 0 bit 4 is write-enabled 1 bit 4 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit 4: timer control/status register w write enable (tcsrwe) bit 4 controls the writing of data to bits 2 and 0 in tcsrw. bit 4 tcsrwe description 0 data cannot be written to bits 2 and 0 (initial value) 1 data can be written to bits 2 and 0 bit 3: bit 2 write inhibit (b2wi) bit 3 controls the writing of data to bit 2 in tcsrw. bit 3 b2wi description 0 bit 2 is write-enabled 1 bit 2 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored.
rev. 4.00, 05/03, page 283 of 562 bit 2: watchdog timer on (wdon) bit 2 enables watchdog timer operation. bit 2 wdon description 0 watchdog timer operation is disabled clearing conditions: reset, or when tcsrwe = 1 and 0 is written in both b2wi and wdon (initial value) 1 watchdog timer operation is enabled setting condition: when tcsrwe = 1 and 0 is written in b2wi and 1 is written in wdon counting starts when this bit is set to 1, and stops when this bit is cleared to 0. bit 1: bit 0 write inhibit (b0wi) bit 1 controls the writing of data to bit 0 in tcsrw. bit 1 b0wi description 0 bit 0 is write-enabled 1 bit 0 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit 0: watchdog timer reset (wrst) bit 0 indicates that tcw has overflowed, generating an internal reset signal. the internal reset signal generated by the overflow resets the entire chip. wrst is cleared to 0 by a reset from the res pin, or when software writes 0. bit 0 wrst description 0 clearing conditions: reset by res pin when tcsrwe = 1, and 0 is written in both bowi and wrst 1 setting condition: when tcw overflows and an internal reset signal is generated
rev. 4.00, 05/03, page 284 of 562 2. timer counter w (tcw) bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 4 tcw4 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w tcw is an 8-bit read/write up-counter, which is incremented by internal clock input. the input clock is /8192 or w/32. the tcw value can always be written or read by the cpu. when tcw overflows from h'ff to h'00, an internal reset signal is generated and wrst is set to 1 in tcsrw. upon reset, tcw is initialized to h'00. 3. clock stop register 2 (ckstpr2) wdckstp pw1ckstp ldckstp pw2ckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the watchdog timer is described here. for details of the other bits, see the sections on the relevant modules. bit 2: watchdog timer module standby mode control (wdckstp) bit 2 controls setting and clearing of module standby mode for the watchdog timer. wdckstp description 0 watchdog timer is set to module standby mode 1 watchdog timer module standby mode is cleared (initial value) note: wdckstp is valid when the wdon bit is cleared to 0 in timer control/status register w (tcsrw). if wdckstp is set to 0 while wdon is set to 1 (during watchdog timer operation), 0 will be set in wdckstp but the watchdog timer will continue its watchdog function and will not enter module standby mode. when the watchdog function ends and wdon is cleared to 0 by software, the wdckstp setting will become valid and the watchdog timer will enter module standby mode.
rev. 4.00, 05/03, page 285 of 562 4. port mode register 2 (pmr2) bit 76543210 pof1 wdcks ncs irq0 initial value11011000 read/write r/w r/w r/w r/w pmr2 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 2. only the bit relating to the watchdog timer is described here. for details of the other bits, see section 8, i/o ports. bit 2: watchdog timer source clock select (wdcks) wdcks description 0 /8192 selected (initial value) 1 w/32 selected 9.6.3 timer operation the watchdog timer has an 8-bit counter (tcw) that is incremented by clock input ( /8192 or w/32). the input clock is selected by the wdcks in port mode register 2 (pmr2): /8192 is selected when wdcks is cleared to 0, and w/32 when set to 1. when tcsrwe = 1 in tcsrw, if 0 is written in b2wi and 1 is simultaneously written in wdon, tcw starts counting up. when the tcw count value reaches h'ff, the next clock input causes the watchdog timer to overflow, and an internal reset signal is generated one base clock ( or sub ) cycle later. the internal reset signal is output for 512 clock cycles of the osc clock. it is possible to write to tcw, causing tcw to count up from the written value. the overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in tcw.
rev. 4.00, 05/03, page 286 of 562 figure 9.18 shows an example of watchdog timer operations. hf8 tcw overflow start hf8 is written in tcw hf8 is written in tcw reset internal reset signal 512 osc clock cycles hff h00 tcw count value example: = 2 mhz and the desired overflow period is 30 ms. the value set in tcw should therefore be 256 8 = 248 (hf8). 2 10 6 30 10 3 = 7.3 8192 figure 9.18 typical watchdog timer operations (example) 9.6.4 watchdog timer operation states table 9.17 summarizes the watchdog timer operation states. table 9.17 watchdog timer operation states operation mode reset active sleep watch subactive subsleep standby module standby tcw reset functions functions halted functions/ halted * halted halted halted tcsrw reset functions functions retained functions/ halted * retained retained retained note: * functions when w/32 is selected as the input clock.
rev. 4.00, 05/03, page 287 of 562 9.7 asynchronous event counter (aec) 9.7.1 overview the asynchronous event counter is incremented by external event clock or internal clock input. 1. features features of the asynchronous event counter are given below. ? can count asynchronous events can count external events input asynchronously without regard to the operation of base clocks and sub . the counter has a 16-bit configuration, enabling it to count up to 65536 (2 16 ) events. ? can also be used as two independent 8-bit event counter channels. ? can be used as single-channel independent 16-bit event counter. ? event/clock input is enabled only when irqaec is high or event counter pwm output (iecpwm) is high. ? both edge sensing can be used for irqaec or event counter pwm output (iecpwm) interrupts. when the asynchronous counter is not used, independent interrupt function use is possible. ? when an event counter pwm is used, event clock input enabling/disabling can be performed automatically in a fixed cycle. ? external event input or a prescaler output clock can be selected by software for the ech and ecl clock sources. /2, /4, or /8 can be selected as the prescaler output clock. ? both edge counting is possible for aevl and aevh. ? counter resetting and halting of the count-up function controllable by software ? automatic interrupt generation on detection of event counter overflow ? use of module standby mode enables this module to be placed in standby mode independently when not used.
rev. 4.00, 05/03, page 288 of 562 2. block diagram figure 9.19 shows a block diagram of the asynchronous event counter. aevh aevl irqaec iecpwm eccr pss eccsr ovh ovl ecpwcrh ecpwdrh aegsr ecpwcrl internal data bus ecpwdrl ech (8 bits) ck ecl (8 bits) ck irrec to cpu interrupt (irrec2) edge sensing circuit edge sensing circuit edge sensing circuit pwm waveform generator /2 /4, /8 /2, /4, /8, /16, /32, /64 notation ecpwcrh: event counter pwm compare register h ecpwdrh: event counter pwm data register h aegsr: input pin edge selection register eccsr: event counter control/status register ech: event counter h ecl: event counter l ecpwcrl: event counter pwm compare register l ecpwdrl: event counter pwm data register l eccr: event counter control register figure 9.19 block diagram of asynchronous event counter
rev. 4.00, 05/03, page 289 of 562 3. pin configuration table 9.18 shows the asynchronous event counter pin configuration. table 9.18 pin configuration name abbr. i/o function asynchronous event input h aevh input event input pin for input to event counter h asynchronous event input l aevl input event input pin for input to event counter l event input enable interrupt input irqaec input input pin for interrupt enabling event input 4. register configuration table 9.19 shows the register configuration of the asynchronous event counter. table 9.19 asynchronous event counter registers name abbr. r/w initial value address event counter pwm compare register h ecpwcrh r/w h'ff h'ff8c event counter pwm compare register l ecpwcrl r/w h'ff h'ff8d event counter pwm data register h ecpwdrh w h'00 h'ff8e event counter pwm data register l ecpwdrl w h'00 h'ff8f input pin edge selection register aegsr r/w h'00 h'ff92 event counter control register eccr r/w h'00 h'ff94 event counter control/status register eccsr r/w h'00 h'ff95 event counter h ech r h'00 h'ff96 event counter l ecl r h'00 h'ff97 clock stop register 2 ckstpr2 r/w h'ff h'fffb
rev. 4.00, 05/03, page 290 of 562 9.7.2 register configurations 1. event counter pwm compare register h (ecpwcrh) bit initial value read/write 7 ecpwcrh7 1 r/w 6 ecpwcrh6 1 r/w 5 ecpwcrh5 1 r/w 4 ecpwcrh4 1 r/w 3 ecpwcrh3 1 r/w 0 ecpwcrh0 1 r/w 2 ecpwcrh2 1 r/w 1 ecpwcrh1 1 r/w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwcrh should not be modified. when changing the conversion period, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwcrh. ecpwcrh is an 8-bit read/write register that sets the event counter pwm waveform conversion period. 2. event counter pwm compare register l (ecpwcrl) bit initial value read/write 7 ecpwcrl7 1 r/w 6 ecpwcrl6 1 r/w 5 ecpwcrl5 1 r/w 4 ecpwcrl4 1 r/w 3 ecpwcrl3 1 r/w 0 ecpwcrl0 1 r/w 2 ecpwcrl2 1 r/w 1 ecpwcrl1 1 r/w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwcrl should not be modified. when changing the conversion period, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwcrl. ecpwcrl is an 8-bit read/write register that sets the event counter pwm waveform conversion period.
rev. 4.00, 05/03, page 291 of 562 3. event counter pwm data register h (ecpwdrh) bit initial value read/write 7 ecpwdrh7 0 w 6 ecpwdrh6 0 w 5 ecpwdrh5 0 w 4 ecpwdrh4 0 w 3 ecpwdrh3 0 w 0 ecpwdrh0 0 w 2 ecpwdrh2 0 w 1 ecpwdrh1 0 w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwdrh should not be modified. when changing the data, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwdrh. ecpwdrh is an 8-bit write-only register that controls event counter pwm waveform generator data. 4. event counter pwm data register l (ecpwdrl) bit initial value read/write 7 ecpwdrl7 0 w 6 ecpwdrl6 0 w 5 ecpwdrl5 0 w 4 ecpwdrl4 0 w 3 ecpwdrl3 0 w 0 ecpwdrl0 0 w 2 ecpwdrl2 0 w 1 ecpwdrl1 0 w note: when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwdrl should not be modified. when changing the data, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwdrl. ecpwdrl is an 8-bit write-only register that controls event counter pwm waveform generator data. 5. input pin edge selection register (aegsr) r - 8 6 n - h n n - y 6 n - / n n - e 6 n - n n - l n n - 6 n - aegsr is an 8-bit read/write register that selects rising, falling, or both edge sensing for the aevh, aevl, and irqaec pins.
rev. 4.00, 05/03, page 292 of 562 bits 7 and 6: aec edge select h bits 7 and 6 select rising, falling, or both edge sensing for the aevh pin. bit 7 ahegs1 bit 6 ahegs0 description 0 0 falling edge on aevh pin is sensed (initial value) 1 rising edge on aevh pin is sensed 1 0 both edges on aevh pin are sensed 1 use prohibited bits 5 and 4: aec edge select l bits 5 and 4 select rising, falling, or both edge sensing for the aevl pin. bit 5 alegs1 bit 4 alegs0 description 0 0 falling edge on aevl pin is sensed (initial value) 1 rising edge on aevl pin is sensed 1 0 both edges on aevl pin are sensed 1 use prohibited bits 3 and 2: irqaec edge select bits 3 and 2 select rising, falling, or both edge sensing for the irqaec pin. bit 3 aiegs1 bit 2 aiegs0 description 0 0 falling edge on irqaec pin is sensed (initial value) 1 rising edge on irqaec pin is sensed 1 0 both edges on irqaec pin are sensed 1 use prohibited
rev. 4.00, 05/03, page 293 of 562 bit 1: event counter pwm enable bit 1 controls enabling/disabling of event counter pwm and selection/deselection of irqaec. bit 1 ecpwme description 0 aec pwm halted, irqaec selected (initial value) 1 aec pwm operation enabled, irqaec deselected bit 0: reserved bit bit 0 is a readable/writable reserved bit. it is initialized to 0 by a reset. note: do not set this bit to 1. 6. event counter control register (eccr) bit initial value read/write 7 ackh1 0 r/w 6 ackh0 0 r/w 5 ackl1 0 r/w 4 ackl0 0 r/w 3 pwck2 0 r/w 0 0 r/w 2 pwck1 0 r/w 1 pwck0 0 r/w eccr performs counter input clock and irqaec/iecpwm control. bits 7 and 6: aec clock select h (ackh1, ackh0) bits 7 and 6 select the clock used by ech. bit 7 ackh1 bit 6 ackh0 description 0 0 aevh pin input (initial value) 1 /2 10 /4 1 /8
rev. 4.00, 05/03, page 294 of 562 bits 5 and 4: aec clock select l (ackl1, ackl0) bits 5 and 4 select the clock used by ecl. bit 5 ackl1 bit 4 ackl0 description 0 0 aevl pin input (initial value) 1 /2 10 /4 1 /8 bits 3 to 1: event counter pwm clock select (pwck2, pwck1, pwck0) bits 3 to 1 select the event counter pwm clock. bit 3 pwck2 bit 2 pwck1 bit 1 pwck0 description 000 /2 (initial value) 1 /4 10 /8 1 /16 1 * 0 /32 1 /64 * : dont care bit 0: reserved bit bit 0 is a readable/writable reserved bit. it is initialized to 0 by a reset. note: do not set this bit to 1.
rev. 4.00, 05/03, page 295 of 562 7. event counter control/status register (eccsr) ovh cuel crch crcl ovl ch2 cueh 76543210 0 0000000 r/w * r/w r/w r/w r/w * r/w r/w r/w bit note: * bits 7 and 6 can only be written with 0, for flag clearing. initial value read/write eccsr is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function. eccsr is initialized to h'00 upon reset. bit 7: counter overflow flag h (ovh) bit 7 is a status flag indicating that ech has overflowed from h'ff to h'00. this flag is set when ech overflows. it is cleared by software but cannot be set by software. ovh is cleared by reading it when set to 1, then writing 0. when ech and ecl are used as a 16-bit event counter with ch2 cleared to 0, ovh functions as a status flag indicating that the 16-bit event counter has overflowed from h'ffff to h'0000. bit 7 ovh description 0 ech has not overflowed (initial value) clearing condition: after reading ovh = 1, cleared by writing 0 to ovh 1 ech has overflowed setting condition: set when ech overflows from hff to h00 bit 6: counter overflow flag l (ovl) bit 6 is a status flag indicating that ecl has overflowed from h'ff to h'00. this flag is set when ecl overflows. it is cleared by software but cannot be set by software. ovl is cleared by reading it when set to 1, then writing 0.
rev. 4.00, 05/03, page 296 of 562 bit 6 ovl description 0 ecl has not overflowed (initial value) clearing condition: after reading ovl = 1, cleared by writing 0 to ovl 1 ecl has overflowed setting condition: set when ecl overflows from h'ff to h'00 bit 5: reserved bit bit 5 is a readable/writable reserved bit. it is initialized to 0 by a reset. bit 4: channel select (ch2) bit 4 selects whether ech and ecl are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels. when ch2 is cleared to 0, ech and ecl function as a 16-bit event counter which is incremented each time an event clock is input to the aevl pin. in this case, the overflow signal from ecl is selected as the ech input clock. when ch2 is set to 1, ech and ecl function as independent 8-bit event counters which are incremented each time an event clock is input to the aevh or aevl pin, respectively. bit 4 ch2 description 0 ech and ecl are used together as a single-channel 16-bit event counter (initial value) 1 ech and ecl are used as two independent 8-bit event counter channels bit 3: count-up enable h (cueh) bit 3 enables event clock input to ech. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ech value is held. the aevh pin or the ecl overflow signal can be selected as the event clock source by bit ch2. bit 3 cueh description 0 ech event clock input is disabled (initial value) ech value is held 1 ech event clock input is enabled
rev. 4.00, 05/03, page 297 of 562 bit 2: count-up enable l (cuel) bit 3 enables event clock input to ecl. when 1 is written to this bit, event clock input is enabled and increments the counter. when 0 is written to this bit, event clock input is disabled and the ecl value is held. bit 2 cuel description 0 ecl event clock input is disabled (initial value) ecl value is held 1 ecl event clock input is enabled bit 1: counter reset control h (crch) bit 1 controls resetting of ech. when this bit is cleared to 0, ech is reset. when 1 is written to this bit, the counter reset is cleared and the ech count-up function is enabled. bit 1 crch description 0 ech is reset (initial value) 1 ech reset is cleared and count-up function is enabled bit 0: counter reset control l (crcl) bit 0 controls resetting of ecl. when this bit is cleared to 0, ecl is reset. when 1 is written to this bit, the counter reset is cleared and the ecl count-up function is enabled. bit 0 crcl description 0 ecl is reset (initial value) 1 ecl reset is cleared and count-up function is enabled 8. event counter h (ech) ech7 ech2 ech1 ech0 ech6 ech5 ech4 ech3 76543210 0 0000000 r rrr rrr r bit initial value read/write ech is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ecl. the external asynchronous event aevh pin, /2, /4, /8, or the overflow signal from lower 8-bit
rev. 4.00, 05/03, page 298 of 562 counter ecl can be selected as the input clock source. ech can be cleared to h'00 by software, and is also initialized to h'00 upon reset. 9. event counter l (ecl) ecl7 ecl2 ecl1 ecl0 ecl6 ecl5 ecl4 ecl3 76543210 0 0000000 r rrr rrr r bit initial value read/write ecl is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ech. the event clock from the external asynchronous event aevl pin, /2, /4, or /8 is used as the input clock source. ecl can be cleared to h'00 by software, and is also initialized to h'00 upon reset. 10. clock stop register 2 (ckstpr2) wdckstp pw1ckstp ldckstp pw2ckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the asynchronous event counter is described here. for details of the other bits, see the sections on the relevant modules. bit 3: asynchronous event counter module standby mode control (aeckstp) bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. aeckstp description 0 asynchronous event counter is set to module standby mode 1 asynchronous event counter module standby mode is cleared (initial value)
rev. 4.00, 05/03, page 299 of 562 9.7.3 operation 1. 16-bit event counter operation when bit ch2 is cleared to 0 in eccsr, ech and ecl operate as a 16-bit event counter. any of four input clock sources /2, /4, /8, or aevl pin inputcan be selected by means of bits ackl1 and ackl0 in eccr. when aevl pin input is selected, input sensing is selected with bits alegs1 and alegs0. the input clock is enabled only when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 9.20 shows an example of the software processing when ech and ecl are used as a 16-bit event counter. start end clear ch2 to 0 set ackl1, ackl0, alegs1, and alegs0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 figure 9.20 example of software processing when using ech and ecl as 16-bit event counter as ch2 is cleared to 0 by a reset, ech and ecl operate as a 16-bit event counter after a reset, and as ackl1 and ackl0 are cleared to 00, the operating clock is asynchronous event input from the aevl pin (using falling edge sensing). when the next clock is input after the count value reaches h'ff in both ech and ecl, ech and ecl overflow from h'ffff to h'0000, the ovh flag is set to 1 in eccsr, the ech and ecl count values each return to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu.
rev. 4.00, 05/03, page 300 of 562 2. 8-bit event counter operation when bit ch2 is set to 1 in eccsr, ech and ecl operate as independent 8-bit event counters. /2, /4, /8, or aevh pin input can be selected as the input clock source for ech by means of bits ackh1 and ackh0 in eccr, and /2, /4, /8, or aevl pin input can be selected as the input clock source for ecl by means of bits ackl1 and ackl0 in eccr. input sensing is selected with bits ahegs1 and ahegs0 when aevh pin input is selected, and with bits alegs1 and alegs0 when aevl pin input is selected. the input clock is enabled only when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 9.21 shows an example of the software processing when ech and ecl are used as 8-bit event counters. start end set ch2 to 1 set ackh1, ackh0, ackl1, ackl0, ahegs1, ahegs0, alegs1, and alegs0 clear cueh, cuel, crch, and crcl to 0 clear ovh to 0 set cueh, cuel, crch, and crcl to 1 figure 9.21 example of software processing when using ech and ecl as 8-bit event counters ech and ecl can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.21. when the next clock is input after the ech count value reaches h'ff, ech overflows, the ovh flag is set to 1 in eccsr, the ech count value returns to h'00, and counting up is restarted. similarly, when the next clock is input after the ecl count value reaches h'ff, ecl overflows, the ovl flag is set to 1 in eccsr, the ecl count value returns to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu.
rev. 4.00, 05/03, page 301 of 562 3. irqaec operation when ecpwme in aegsr is 0, the ech and ecl input clocks are enabled only when irqaec is high. when irqaec is low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled from outside by controlling irqaec. in this case, ech and ecl cannot be controlled individually. irqaec can also operate as an interrupt source. in this case the vector number is 6 and the vector addresses are h'000c and h'000d. interrupt enabling is controlled by ienec2 in ienr1. when an irqaec interrupt is generated, irr1 interrupt request flag irrec2 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge sensing can be selected for the irqaec input pin, with bits aiags1 and aiags0 in aegsr. 4. event counter pwm operation when ecpwme in aegsr is 1, the ech and ecl input clocks are enabled only when event counter pwm output (iecpwm) is high. when iecpwm is low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled cyclically from outside by controlling event counter pwm. in this case, ech and ecl cannot be controlled individually. iecpwm can also operate as an interrupt source. in this case the vector number is 6 and the vector addresses are h'000c and h'000d. interrupt enabling is controlled by ienec2 in ienr1. when an iecpwm interrupt is generated, irr1 interrupt request flag irrec2 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge detection can be selected for iecpwm interrupt sensing with bits aiags1 and aiags0 in aegsr.
rev. 4.00, 05/03, page 302 of 562 figure 9.22 and table 9.20 show examples of event counter pwm operation. t off = t (n dr +1) t on t cm = t (n cm +1) t on : clock input enabled time t off : clock input disabled time t cm : one conversion period t : ecpwm input clock cycle n dr : value of ecpwdrh and ecpwdrl fixed high when ndr = hffff n cm : value of ecpwcrh and ecpwcrl figure 9.22 event counter operation waveform note: n dr and n cm above must be set so that n dr < n cm . if the settings do not satisfy this condition, do not set ecpwme in aegsr to 1. table 9.20 examples of event counter pwm operation conditions: f osc = 4 mhz, f = 2 mhz, high-speed active mode, ecpwcr value (n cm ) = h'7a11, ecpwdr value (n dr ) = h'16e3 clock source selection clock source cycle (t) * ecpwcr value (n cm ) ecpwdr value (n dr ) t off = t (n dr + 1) t cm = t (n cm + 1) t on = t cm C t off /2 1 s 5.86 ms 31.25 ms 25.39 ms /4 2 s h'7a11 d'31249 h'16e3 d'5859 11.72 ms 62.5 ms 50.78 ms /8 4 s 23.44 ms 125.0 ms 101.56 ms /16 8 s 46.88 ms 250.0 ms 203.12 ms /32 16 s 93.76 ms 500.0 ms 406.24 ms /64 32 s 187.52 ms 1000.0 ms 812.48 ms note: * t off minimum width 5. clock input enable/disable function operation the clock input to the event counter can be controlled by the irqaec pin when ecpwme in aegsr is 0, and by event counter pwm output iecpwm when ecpwme in aegsr is 1. as this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending the irqaec or iecpwm timing.
rev. 4.00, 05/03, page 303 of 562 figure 9.23 shows an example of the operation of this function. clock stopped n+2 n+3 n+4 n+5 n+6 n n+1 edge generated by clock return input event irqaec or iecpwm actually counted clock source counter value figure 9.23 example of clock control operation 9.7.4 asynchronous event counter operation modes asynchronous event counter operation modes are shown in table 9.21. table 9.21 asynchronous event counter operation modes operation mode reset active sleep watch subactive subsleep standby module standby aegsr reset functions functions retained * 1 functions functions retained * 1 retained eccr reset functions functions retained * 1 functions functions retained * 1 retained eccsr reset functions functions retained * 1 functions functions retained * 1 retained ech reset functions functions functions * 1 * 2 functions * 2 functions * 2 functions * 1 * 2 halted ecl reset functions functions functions * 1 * 2 functions * 2 functions * 2 functions * 1 * 2 halted ieqaec reset functions functions retained * 3 functions functions retained * 3 retained * 4 event counter pwm reset functions functions retained retained retained retained retained notes: * 1 when an asynchronous external event is input, the counter increments but the counter overflow h/l flags are not affected. * 2 operates when asynchronous external events are selected; halted and retained otherwise. * 3 clock control by irqaec operates, but interrupts do not. * 4 as the clock is stopped in module standby mode, irqaec has no effect.
rev. 4.00, 05/03, page 304 of 562 9.7.5 application notes 1. when reading the values in ech and ecl, the correct value will not be returned if the event counter increments during the read operation. therefore, if the counter is being used in the 8- bit mode, clear bits cueh and cuel in eccsr to 0 before reading ech or ecl. if the counter is being used in the 16-bit mode, clear cuel only to 0 before reading ech or ecl. 2. use a clock with a frequency of up to 16 mhz for input to the aevh and aevl pins, and ensure that the high and low widths of the clock are at least 30 ns. the duty cycle is immaterial. mode maximum aevh/aevl pin input clock frequency active (high-speed), sleep (high-speed) 16 mhz active (medium-speed), sleep (medium-speed) ( /16) ( /32) ( /64) f osc = 1 mhz to 4 mhz ( /128) 2 ? f osc f osc 1/2 ? f osc 1/4 ? f osc watch, subactive, subsleep, standby ( w/2) ( w/4) w = 32.768 khz or 38.4 khz ( w/8) 1000 khz 500 khz 250 khz 3. when using the clock in the 16-bit mode, set cueh to 1 first, then set crch to 1 in eccsr. or, set cueh and crch simultaneously before inputting the clock. after that, do not change the cueh value while using in the 16-bit mode. otherwise, an error counter increment may occur. also, to reset the counter, clear crch and crcl to 0 simultaneously or clear crcl and crch to 0 sequentially, in that order. 4. when ecpwme in aegsr is 1, event counter pwm is operating and therefore ecpwcrh, ecpwcrl, ecpwdrh, and ecpwdrl should not be modified. when changing the data, event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying these registers. 5. the event counter pwm data register and event counter pwm compare register must be set so that event counter pwm data register < event counter pwm compare register. if the settings do not satisfy this condition, do not set ecpwme to 1 in aegsr. 6. as synchronization is established internally when an irqaec interrupt is generated, a maximum error of 1 t cyc will occur between clock halting and interrupt acceptance.
rev. 4.00, 05/03, page 305 of 562 section 10 serial communication interface 10.1 overview the h8/38024 group is provided with one serial communication interface, sci3. serial communication interface 3 (sci3) can carry out serial data communication in either asynchronous or synchronous mode. it is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. 10.1.1 features features of sci3 are listed below. ? choice of asynchronous or synchronous mode for serial data communication ? asynchronous mode serial data communication is performed asynchronously, with synchronization provided character by character. in this mode, serial data can be exchanged with standard asynchronous communication lsis such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a multiprocessor communication function is also provided, enabling serial data communication among processors. there is a choice of 16 data transfer formats. data length 7, 8, 5 bits stop bit length 1 or 2 bits parity even, odd, or none multiprocessor bit 1 or 0 receive error detection parity, overrun, and framing errors break detection break detected by reading the rxd 32 pin level directly when a framing error occurs ? synchronous mode serial data communication is synchronized with a clock. in this mode, serial data can be exchanged with another lsi that has a synchronous communication function. data length 8 bits receive error detection overrun errors
rev. 4.00, 05/03, page 306 of 562 ? full-duplex communication separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. the transmission and reception units are both double-buffered, allowing continuous transmission and reception. ? on-chip baud rate generator, allowing any desired bit rate to be selected ? choice of an internal or external clock as the transmit/receive clock source ? six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error
rev. 4.00, 05/03, page 307 of 562 10.1.2 block diagram figure 10.1 shows a block diagram of sci3. clock txd 32 rxd 32 sck brr smr scr3 ssr tdr rdr tsr rsr spcr transmit/receive control circuit internal data bus notation: rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: spcr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter serial port control register interrupt request (tei, txi, rxi, eri) 32 internal clock ( /64, /16, w /2, ) external clock brc baud rate generator figure 10.1 sci3 block diagram
rev. 4.00, 05/03, page 308 of 562 10.1.3 pin configuration table 10.1 shows the sci3 pin configuration. table 10.1 pin configuration name abbr. i/o function sci3 clock sck 32 i/o sci3 clock input/output sci3 receive data input rxd 32 input sci3 receive data input sci3 transmit data output txd 32 output sci3 transmit data output 10.1.4 register configuration table 10.2 shows the sci3 register configuration. table 10.2 registers name abbr. r/w initial value address serial mode register smr r/w h'00 h'ffa8 bit rate register brr r/w h'ff h'ffa9 serial control register 3 scr3 r/w h'00 h'ffaa transmit data register tdr r/w h'ff h'ffab serial status register ssr r/w h'84 h'ffac receive data register rdr r h'00 h'ffad transmit shift register tsr protected receive shift register rsr protected bit rate counter brc protected clock stop register 1 ckstpr1 r/w h'ff h'fffa serial port control register spcr r/w h'ff91
rev. 4.00, 05/03, page 309 of 562 10.2 register descriptions 10.2.1 receive shift register (rsr) bit read/write 7 6 5 4 3 0 2 1 rsr is a register used to receive serial data. serial data input to rsr from the rxd 32 pin is set in the order in which it is received, starting from the lsb (bit 0), and converted to parallel data. when one byte of data is received, it is transferred to rdr automatically. rsr cannot be read or written directly by the cpu. 10.2.2 receive data register (rdr) bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r rdr is an 8-bit register that stores received serial data. when reception of one byte of data is finished, the received data is transferred from rsr to rdr, and the receive operation is completed. rsr is then able to receive data. rsr and rdr are double-buffered, allowing consecutive receive operations. rdr is a read-only register, and cannot be written by the cpu. rdr is initialized to h'00 upon reset, and in standby, module standby or watch mode.
rev. 4.00, 05/03, page 310 of 562 10.2.3 transmit shift register (tsr) bit read/write 7 6 5 4 3 0 2 1 tsr is a register used to transmit serial data. transmit data is first transferred from tdr to tsr, and serial data transmission is carried out by sending the data to the txd 32 pin in order, starting from the lsb (bit 0). when one byte of data is transmitted, the next byte of transmit data is transferred to tdr, and transmission started, automatically. data transfer from tdr to tsr is not performed if no data has been written to tdr (if bit tdre is set to 1 in the serial status register (ssr)). tsr cannot be read or written directly by the cpu. 10.2.4 transmit data register (tdr) bit initial value read/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w tdr is an 8-bit register that stores transmit data. when tsr is found to be empty, the transmit data written in tdr is transferred to tsr, and serial data transmission is started. continuous transmission is possible by writing the next transmit data to tdr during tsr serial data transmission. tdr can be read or written by the cpu at any time. tdr is initialized to h'ff upon reset, and in standby, module standby, or watch mode.
rev. 4.00, 05/03, page 311 of 562 10.2.5 serial mode register (smr) bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 pm 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w smr is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. smr can be read or written by the cpu at any time. smr is initialized to h'00 upon reset, and in standby, module standby, or watch mode. bit 7: communication mode (com) bit 7 selects whether sci3 operates in asynchronous mode or synchronous mode. bit 7 com description 0 asynchronous mode (initial value) 1 synchronous mode bit 6: character length (chr) bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. in synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. bit 6 chr description 0 8-bit data/5-bit data * 2 (initial value) 1 7-bit data * 1 /5-bit data * 2 notes: * 1 when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. * 2 when 5-bit data is selected, set both pe and mp to 1. the three most significant bits (bits 7, 6, and 5) of tdr are not transmitted.
rev. 4.00, 05/03, page 312 of 562 bit 5: parity enable (pe) bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. in synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. bit 5 pe description 0 parity bit addition and checking disabled * 2 (initial value) 1 parity bit addition and checking enabled * 1/ * 2 notes: * 1 when pe is set to 1, even or odd parity, as designated by bit pm, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit pm. * 2 for the case where 5-bit data is selected, see table 10.11. bit 4: parity mode (pm) bit 4 selects whether even or odd parity is to be used for parity addition and checking. the pm bit setting is only valid in asynchronous mode when bit pe is set to 1, enabling parity bit addition and checking. the pm bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled. bit 4 pm description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: * 1 when even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. * 2 when odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number.
rev. 4.00, 05/03, page 313 of 562 bit 3: stop bit length (stop) bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. when synchronous mode is selected the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: * 1 in transmission, a single 1 bit (stop bit) is added at the end of a transmit character. * 2 in transmission, two 1 bits (stop bits) are added at the end of a transmit character. in reception, only the first of the received stop bits is checked, irrespective of the stop bit setting. if the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. bit 2: multiprocessor mode (mp) bit 2 enables or disables the multiprocessor communication function. when the multiprocessor communication function is enabled, the parity settings in the pe and pm bits are invalid. the mp bit setting is only valid in asynchronous mode. when synchronous mode is selected the mp bit should be set to 0. for details on the multiprocessor communication function, see section 10.3.4, multiprocessor communication function. bit 2 mp description 0 multiprocessor communication function disabled * (initial value) 1 multiprocessor communication function enabled * note: * for the case where 5-bit data is selected, see table 10.11.
rev. 4.00, 05/03, page 314 of 562 bits 1 and 0: clock select 1, 0 (cks1, cks0) bits 1 and 0 choose /64, /16, w/2, or as the clock source for the baud rate generator. for the relation between the clock source, bit rate register setting, and baud rate, see section 10.2.8, bit rate register (brr). bit 1 cks1 bit 0 cks0 description 00 clock (initial value) 01 w/2 clock * 1 / w clock * 2 10 /16 clock 11 /64 clock notes: * 1 w/2 clock in active (medium-speed/high-speed) mode and sleep mode * 2 w clock in subactive mode and subsleep mode. in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. 10.2.6 serial control register 3 (scr3) bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w scr3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. scr3 can be read or written by the cpu at any time. scr3 is initialized to h'00 upon reset, and in standby, module standby or watch mode.
rev. 4.00, 05/03, page 315 of 562 bit 7: transmit interrupt enable (tie) bit 7 selects enabling or disabling of the transmit data empty interrupt request (txi) when transmit data is transferred from the transmit data register (tdr) to the transmit shift register (tsr), and bit tdre in the serial status register (ssr) is set to 1. txi can be released by clearing bit tdre or bit tie to 0. bit 7 tie description 0 transmit data empty interrupt request (txi) disabled (initial value) 1 transmit data empty interrupt request (txi) enabled bit 6: receive interrupt enable (rie) bit 6 selects enabling or disabling of the receive data full interrupt request (rxi) and the receive error interrupt request (eri) when receive data is transferred from the receive shift register (rsr) to the receive data register (rdr), and bit rdrf in the serial status register (ssr) is set to 1. there are three kinds of receive error: overrun, framing, and parity. rxi and eri can be released by clearing bit rdrf or the fer, per, or oer error flag to 0, or by clearing bit rie to 0. bit 6 rie description 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled (initial value) 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled bit 5: transmit enable (te) bit 5 selects enabling or disabling of the start of transmit operation. bit 5 te description 0 transmit operation disabled * 1 (txd32 pin is i/o port) (initial value) 1 transmit operation enabled * 2 (txd32 pin is transmit data pin) notes: * 1 bit tdre in ssr is fixed at 1. * 2 when transmit data is written to tdr in this state, bit tdre in ssr is cleared to 0 and serial data transmission is started. be sure to carry out serial mode register (smr) settings, and setting of bit spc32 in spcr, to decide the transmission format before setting bit te to 1.
rev. 4.00, 05/03, page 316 of 562 bit 4: receive enable (re) bit 4 selects enabling or disabling of the start of receive operation. bit 4 re description 0 receive operation disabled * 1 (rxd32 pin is i/o port) (initial value) 1 receive operation enabled * 2 (rxd32 pin is receive data pin) notes: * 1 note that the rdrf, fer, per, and oer flags in ssr are not affected when bit re is cleared to 0, and retain their previous state. * 2 in this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. be sure to carry out serial mode register (smr) settings to decide the reception format before setting bit re to 1. bit 3: multiprocessor interrupt enable (mpie) bit 3 selects enabling or disabling of the multiprocessor interrupt request. the mpie bit setting is only valid when asynchronous mode is selected and reception is carried out with bit mp in smr set to 1. the mpie bit setting is invalid when bit com is set to 1 or bit mp is cleared to 0. bit 3 mpie description 0 multiprocessor interrupt request disabled (normal receive operation) (initial value) clearing condition: when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled * note: * receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and oer status flags in ssr is not performed. rxi, eri, and setting of the rdrf, fer, and oer flags in ssr, are disabled until data with the multiprocessor bit set to 1 is received. when a receive character with the multiprocessor bit set to 1 is received, bit mpbr in ssr is set to 1, bit mpie is automatically cleared to 0, and rxi and eri requests (when bits tie and rie in serial control register 3 (scr3) are set to 1) and setting of the rdrf, fer, and oer flags are enabled.
rev. 4.00, 05/03, page 317 of 562 bit 2: transmit end interrupt enable (teie) bit 2 selects enabling or disabling of the transmit end interrupt request (tei) if there is no valid transmit data in tdr when msb data is to be sent. bit 2 teie description 0 transmit end interrupt request (tei) disabled (initial value) 1 transmit end interrupt request (tei) enabled * note: * tei can be released by clearing bit tdre to 0 and clearing bit tend to 0 in ssr, or by clearing bit teie to 0. bits 1 and 0: clock enable 1 and 0 (cke1, cke0) bits 1 and 0 select the clock source and enabling or disabling of clock output from the sck 32 pin. the combination of cke1 and cke0 determines whether the sck 32 pin functions as an i/o port, a clock output pin, or a clock input pin. the cke0 bit setting is only valid in case of internal clock operation (cke1 = 0) in asynchronous mode. in synchronous mode, or when external clock operation is used (cke1 = 1), bit cke0 should be cleared to 0. after setting bits cke1 and cke0, set the operating mode in the serial mode register (smr). for details on clock source selection, see table 10.9 in section 10.3.1, overview. description bit 1 cke1 bit 0 cke0 communication mode clock source sck 32 pin function 0 0 asynchronous internal clock i/o port * 1 synchronous internal clock serial clock output * 1 0 1 asynchronous internal clock clock output * 2 synchronous reserved 1 0 asynchronous external clock clock input * 3 synchronous external clock serial clock input 1 1 asynchronous reserved synchronous reserved notes: * 1 initial value * 2 a clock with the same frequency as the bit rate is output. * 3 input a clock with a frequency 16 times the bit rate.
rev. 4.00, 05/03, page 318 of 562 10.2.7 serial status register (ssr) bit initial value read/write 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 oer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r note: * only a write of 0 for flag clearing is possible. ssr is an 8-bit register containing status flags that indicate the operational status of sci3, and multiprocessor bits. ssr can be read or written to by the cpu at any time, but 1 cannot be written to bits tdre, rdrf, oer, per, and fer. bits tend and mpbr are read-only bits, and cannot be modified. ssr is initialized to h'84 upon reset, and in standby, module standby, or watch mode. bit 7: transmit data register empty (tdre) bit 7 indicates that transmit data has been transferred from tdr to tsr. bit 7 tdre description 0 transmit data written in tdr has not been transferred to tsr clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmit data has not been written to tdr, or transmit data written in tdr has been transferred to tsr setting conditions: when bit te in scr3 is cleared to 0 when data is transferred from tdr to tsr (initial value)
rev. 4.00, 05/03, page 319 of 562 bit 6: receive data register full (rdrf) bit 6 indicates that received data is stored in rdr. bit 6 rdrf description 0 there is no receive data in rdr (initial value) clearing conditions: after reading rdrf = 1, cleared by writing 0 to rdrf when rdr data is read by an instruction 1 there is receive data in rdr setting condition: when reception ends normally and receive data is transferred from rsr to rdr note: if an error is detected in the receive data, or if the re bit in scr3 has been cleared to 0, rdr and bit rdrf are not affected and retain their previous state. note that if data reception is completed while bit rdrf is still set to 1, an overrun error (oer) will result and the receive data will be lost. bit 5: overrun error (oer) bit 5 indicates that an overrun error has occurred during reception. bit 5 oer description 0 reception in progress or completed * 1 (initial value) clearing condition: after reading oer = 1, cleared by writing 0 to oer 1 an overrun error has occurred during reception * 2 setting condition: when reception is completed with rdrf set to 1 notes: * 1 when bit re in scr3 is cleared to 0, bit oer is not affected and retains its previous state. * 2 rdr retains the receive data it held before the overrun error occurred, and data received after the error is lost. reception cannot be continued with bit oer set to 1, and in synchronous mode, transmission cannot be continued either.
rev. 4.00, 05/03, page 320 of 562 bit 4: framing error (fer) bit 4 indicates that a framing error has occurred during reception in asynchronous mode. bit 4 fer description 0 reception in progress or completed * 1 (initial value) clearing condition: after reading fer = 1, cleared by writing 0 to fer 1 a framing error has occurred during reception setting condition: when the stop bit at the end of the receive data is checked for a value of 1 at the end of reception, and the stop bit is 0 * 2 notes: * 1 when bit re in scr3 is cleared to 0, bit fer is not affected and retains its previous state. * 2 note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. when a framing error occurs the receive data is transferred to rdr but bit rdrf is not set. reception cannot be continued with bit fer set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1. bit 3: parity error (per) bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. bit 3 per description 0 reception in progress or completed * 1 (initial value) clearing condition: after reading per = 1, cleared by writing 0 to per 1 a parity error has occurred during reception * 2 setting condition: when the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit pm in the serial mode register (smr) notes: * 1 when bit re in scr3 is cleared to 0, bit per is not affected and retains its previous state. * 2 receive data in which a parity error has occurred is still transferred to rdr, but bit rdrf is not set. reception cannot be continued with bit per set to 1. in synchronous mode, neither transmission nor reception is possible when bit fer is set to 1.
rev. 4.00, 05/03, page 321 of 562 bit 2: transmit end (tend) bit 2 indicates that bit tdre is set to 1 when the last bit of a transmit character is sent. bit 2 is a read-only bit and cannot be modified. bit 2 tend description 0 transmission in progress clearing conditions: after reading tdre = 1, cleared by writing 0 to tdre when data is written to tdr by an instruction 1 transmission ended (initial value) setting conditions: when bit te in scr3 is cleared to 0 when bit tdre is set to 1 when the last bit of a transmit character is sent bit 1: multiprocessor bit receive (mpbr) bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. bit 1 is a read-only bit and cannot be modified. bit 1 mpbr description 0 data in which the multiprocessor bit is 0 has been received * (initial value) 1 data in which the multiprocessor bit is 1 has been received note: * when bit re is cleared to 0 in scr3 with the multiprocessor format, bit mpbr is not affected and retains its previous state. bit 0: multiprocessor bit transfer (mpbt) bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous mode. the bit mpbt setting is invalid when synchronous mode is selected, when the multiprocessor communication function is disabled, and when not transmitting. bit 0 mpbt description 0 a 0 multiprocessor bit is transmitted (initial value) 1 a 1 multiprocessor bit is transmitted
rev. 4.00, 05/03, page 322 of 562 10.2.8 bit rate register (brr) bit initial value read/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w brr is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 of the serial mode register (smr). brr can be read or written by the cpu at any time. brr is initialized to h'ff upon reset, and in standby, module standby, or watch mode. table 10.3 shows examples of brr settings in asynchronous mode. the values shown are for active (high-speed) mode. table 10.3 examples of brr settings for various bit rates (asynchronous mode) (1) osc 32.8 khz 38.4 khz 2 mhz 2.4576 mhz 4 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 21C0.83 150 030 2120.16330 2250.16 200 0 2 0 0 155 0.16 3 2 0 250 0 124 0 0 153 C0.26 0 249 0 300 cannot be used, as error exceeds 3% 010 01030.16310 2120.16 600 0 0 0 0 51 0.16 3 0 0 0 103 0.16 1200 0 25 0.16 2 1 0 0 51 0.16 2400 0 12 0.16 2 0 0 0 25 0.16 4800 0 7 0 0 12 0.16 9600 0 3 0 19200 0 1 0 31250 0 0 0 0 1 0 38400 0 0 0
rev. 4.00, 05/03, page 323 of 562 table 10.3 examples of brr settings for various bit rates (asynchronous mode) (2) osc 10 mhz 16 mhz bit rate (bit/s) n n error (%) n n error (%) 110 2 88 C0.25 2 141 C0.02 150 2 64 0.16 2 103 0.16 200 2 48 C0.35 2 77 0.16 250 2 38 0.16 2 62 C0.79 300 2 51 0.16 600 2 25 0.16 1200 0 129 0.16 0 207 0.16 2400 0 64 0.16 0 103 0.16 4800 0 51 0.16 9600 0 25 0.16 19200 0 12 0.16 31250 0 4 0 0 7 0 38400 notes: 1. the setting should be made so that the error is not more than 1%. 2. the value set in brr is given by the following equation: osc n = (64 2 2n b) C 1 where b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.4.) 3. the error in table 10.3 is the value obtained from the following equation, rounded to two decimal places. b (rate obtained from n, n, osc) C r(bit rate in left-hand column in table 10.3.) error (%) = r (bit rate in left-hand column in table 10.3.) 100
rev. 4.00, 05/03, page 324 of 562 table 10.4 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w/2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: * 1 w/2 clock in active (medium-speed/high-speed) mode and sleep mode * 2 w clock in subactive mode and subsleep mode in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only. table 10.5 shows the maximum bit rate for each frequency. the values shown are for active (high-speed) mode. table 10.5 maximum bit rate for each frequency (asynchronous mode) setting osc (mhz) maximum bit rate (bit/s) nn 0.0384 * 600 0 0 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 10 156250 0 0 16 250000 0 0 note: * when smr is set up to cks1 = 0, cks0 = 1.
rev. 4.00, 05/03, page 325 of 562 table 10.6 shows examples of brr settings in synchronous mode. the values shown are for active (high-speed) mode. table 10.6 examples of brr settings for various bit rates (synchronous mode) (1) osc 38.4 khz 2 mhz 4 mhz bit rate (bit/s) n n error n n error n n error 200 0 230 250 2 1240 300 2 0 0 500 1k 0 249 0 2.5k 0 99 0 0 199 0 5k 04900990 10k 02400490 25k 0900190 50k 040090 100k 0 4 0 250k 0 0 0 0 1 0 500k 0 0 0 1m
rev. 4.00, 05/03, page 326 of 562 table 10.6 examples of brr settings for various bit rates (synchronous mode) (2) osc 10 mhz 16 mhz bit rate (bit/s) n n error n n error 200 250 3 1240 300 500 2 2490 1k 2 1240 2.5k 2 490 5k 0 249 0 2 24 0 10k 0 124 0 0 199 0 25k 04900790 50k 02400390 100k 0 190 250k 040070 500k 0 3 0 1m 0 1 0 blank: cannot be set. : a setting can be made, but an error will result. notes: the value set in brr is given by the following equation: osc n = (8 2 2n b) C 1 where b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.7.)
rev. 4.00, 05/03, page 327 of 562 table 10.7 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: * 1 w/2 clock in active (medium-speed/high-speed) mode and sleep mode * 2 w clock in subactive mode and subsleep mode in subactive or subsleep mode, sci3 can be operated when cpu clock is w/2 only.
rev. 4.00, 05/03, page 328 of 562 10.2.9 clock stop register 1 (ckstpr1) tfckstptcckstptackstp s32ckstpadckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bits relating to sci3 are described here. for details of the other bits, see the sections on the relevant modules. bit 5: sci3 module standby mode control (s32ckstp) bit 5 controls setting and clearing of module standby mode for sci3. s32ckstp description 0 sci3 is set to module standby mode 1 sci3 module standby mode is cleared (initial value) note: all sci3 register is initialized in module standby mode. 10.2.10 serial port control register (spcr) bit initial value read/write 7 1 6 1 5 spc32 0 r/w 4 w 3 scinv3 0 r/w 0 w 2 scinv2 0 r/w 1 w spcr is an 8-bit readable/writable register that performs rxd 32 and txd 32 pin input/output data inversion switching. bits 7 and 6: reserved bits bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
rev. 4.00, 05/03, page 329 of 562 bit 5: p4 2 /txd 32 pin function switch (spc32) this bit selects whether pin p4 2 /txd 32 is used as p4 2 or as txd 32 . bit 5 spc32 description 0 functions as p4 2 i/o pin (initial value) 1 functions as txd 32 output pin * note: * set the te bit in scr3 after setting this bit to 1. bit 4: reserved bit bit 4 is reserved; only 0 can be written to this bit. bit 3: txd 32 pin output data inversion switch bit 3 specifies whether or not txd 32 pin output data is to be inverted. bit 3 scinv3 description 0txd 32 output data is not inverted (initial value) 1txd 32 output data is inverted bit 2: rxd 32 pin input data inversion switch bit 2 specifies whether or not rxd 32 pin input data is to be inverted. bit 2 scinv2 description 0rxd 32 input data is not inverted (initial value) 1rxd 32 input data is inverted bits 1 and 0: reserved bits bits 1 and 0 are reserved; only 0 can written to these bits.
rev. 4.00, 05/03, page 330 of 562 10.3 operation 10.3.1 overview sci3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. the serial mode register (smr) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8. the clock source for sci3 is determined by bit com in smr and bits cke1 and cke0 in scr3, as shown in table 10.9. 1. asynchronous mode ? choice of 5-, 7-, or 8-bit data length ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (the combination of these parameters determines the data transfer format and the character length.) ? framing error (fer), parity error (per), overrun error (oer), and break detection during reception ? choice of internal or external clock as the clock source when internal clock is selected: sci3 operates on the baud rate generator clock, and a clock with the same frequency as the bit rate can be output. when external clock is selected: a clock with a frequency 16 times the bit rate must be input. (the on-chip baud rate generator is not used.) 2. synchronous mode ? data transfer format: fixed 8-bit data length ? overrun error (oer) detection during reception ? choice of internal or external clock as the clock source when internal clock is selected: sci3 operates on the baud rate generator clock, and a serial clock is output. when external clock is selected: the on-chip baud rate generator is not used, and sci3 operates on the input serial clock.
rev. 4.00, 05/03, page 331 of 562 table 10.8 smr settings and corresponding data transfer formats smr data transfer format bit 7 com bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multiprocessor bit parity bit stop bit length 00000 8-bit datano no1 bit 12 bits 10 asynchronous mode yes 1 bit 12 bits 1 0 0 7-bit data no 1 bit 12 bits 10 yes1 bit 12 bits 0 1 0 0 8-bit data yes no 1 bit 12 bits 1 0 5-bit data no 1 bit 12 bits 1 0 0 7-bit data yes 1 bit 12 bits 1 0 5-bit data no yes 1 bit 12 bits 1 * 0 ** synchronous mode 8-bit data no no no * : dont care
rev. 4.00, 05/03, page 332 of 562 table 10.9 smr and scr3 settings and clock source selection smr scr3 bit 7 bit 1 bit 0 transmit/receive clock com cke1 cke0 mode clock source sck 32 pin function 0 0 0 internal i/o port (sck 32 pin not used) 1 asynchronous mode outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency 16 times bit rate 1 0 0 internal outputs serial clock 10 synchronous mode external inputs serial clock 0 1 1 reserved (do not specify these combinations) 10 1 11 1 3. interrupts and continuous transmission/reception sci3 can carry out continuous reception using rxi and continuous transmission using txi. these interrupts are shown in table 10.10. table 10.10 transmit/receive interrupts interrupt flags interrupt request conditions notes rxi rdrf rie when serial reception is performed normally and receive data is transferred from rsr to rdr, bit rdrf is set to 1, and if bit rie is set to 1 at this time, rxi is enabled and an interrupt is requested. (see figure 10.2(a).) the rxi interrupt routine reads the receive data transferred to rdr and clears bit rdrf to 0. continuous reception can be performed by repeating the above operations until reception of the next rsr data is completed. txi tdre tie when tsr is found to be empty (on completion of the previous transmission) and the transmit data placed in tdr is transferred to tsr, bit tdre is set to 1. if bit tie is set to 1 at this time, txi is enabled and an interrupt is requested. (see figure 10.2(b).) the txi interrupt routine writes the next transmit data to tdr and clears bit tdre to 0. continuous transmission can be performed by repeating the above operations until the data transferred to tsr has been transmitted. tei tend teie when the last bit of the character in tsr is transmitted, if bit tdre is set to 1, bit tend is set to 1. if bit teie is set to 1 at this time, tei is enabled and an interrupt is requested. (see figure 10.2(c).) tei indicates that the next transmit data has not been written to tdr when the last bit of the transmit character in tsr is sent.
rev. 4.00, 05/03, page 333 of 562 rdr rsr (reception in progress) rdrf = 0 rxd 32 pin rdr rsr (reception completed, transfer) rdrf 1 (rxi request when rie = 1) rxd 32 pin figure 10.2(a) rdrf setting and rxi interrupt tdr (next transmit data) tsr (transmission in progress) tdre = 0 txd 32 pin tdr tsr (transmission completed, transfer) tdre 1 (txi request when tie = 1) txd 32 pin figure 10.2(b) tdre setting and txi interrupt tdr tsr (transmission in progress) tend = 0 txd 32 pin tdr tsr (reception completed) tend 1 (tei request when teie = 1) txd 32 pin figure 10.2(c) tend setting and tei interrupt
rev. 4.00, 05/03, page 334 of 562 10.3.2 operation in asynchronous mode in asynchronous mode, serial communication is performed with synchronization provided character by character. a start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. sci3 has separate transmission and reception units, allowing full-duplex communication. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.3. serial data start bit 1 bit transmit/receive data parity bit stop bit(s) 5, 7, or 8 bits one transfer data unit (character or frame) 1 bit or none 1 or 2 bits mark state 1 (msb) (lsb) figure 10.3 data format in asynchronous communication in asynchronous communication, the communication line is normally in the mark state (high level). sci3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. one transfer data character consists of a start bit (low level), followed by transmit/receive data (lsb-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. the data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.
rev. 4.00, 05/03, page 335 of 562 table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. the format is selected by the settings in the serial mode register (smr). table 10.11 data transfer formats (asynchronous mode) 1 chr 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 pe mp stop 2 3 4 5 8-bit data serial data transfer format and frame length smr stop s 6789101112 8-bit data s 7-bit data stopstop s stop 7-bit data s stopstop 5-bit data s stop 5-bit data s stopstop 8-bit data p s stop 8-bit data p s stopstop 8-bit data mpb s stop 8-bit data mpb s stopstop 7-bit data pstop s stop 7-bit data stop s 5-bit data stop p p p s 5-bit data stopstop s notation: s: stop: p: mpb: start bit stop bit parity bit multiprocessor bit stop 7-bit data stop s 7-bit data stop mpb mpb s
rev. 4.00, 05/03, page 336 of 562 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 32 pin can be selected as the sci3 transmit/receive clock. the selection is made by means of bit com in smr and bits sce1 and cke0 in scr3. see table 10.9 for details on clock source selection. when an external clock is input at the sck 32 pin, the clock frequency should be 16 times the bit rate. when sci3 operates on an internal clock, the clock can be output at the sck 32 pin. in this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10.4. 1 character (1 frame) 0 d0d1d2d3d4d5d6d70/1 1 1 clock serial data figure 10.4 phase relationship between output clock and transfer data (asynchronous mode) (8-bit data, parity, 2 stop bits) 3. data transfer operations ? sci3 initialization before data is transferred on sci3, bits te and re in scr3 must first be cleared to 0, and then sci3 must be initialized as follows. note: if the operation mode or data transfer format is changed, bits te and re must first be cleared to 0. when bit te is cleared to 0, bit tdre is set to 1. note that the rdrf, per, fer, and oer flags and the contents of rdr are retained when re is cleared to 0. when an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. when an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization.
rev. 4.00, 05/03, page 337 of 562 figure 10.5 shows an example of a flowchart for initializing sci3. start end clear bits te and re to 0 in scr3 1 2 3 set bits cke1 and cke0 set data transfer format in smr set bit spc32 to 1 in spcr set value in brr no wait yes 4 set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in scr3 has 1-bit period elapsed? set clock selection in scr3. be sure to clear the other bits to 0. if clock output is selected in asynchronous mode, the clock is output immediately after setting bits cke1 and cke0. if clock output is selected for reception in synchronous mode, the clock is output immediately after bits cke1, cke0, and re are set to 1. set the data transfer format in the serial mode register (smr). write the value corresponding to the transfer rate in brr. this operation is not necessary when an external clock is selected. wait for at least one bit period, then set bits tie, rie, mpie, and teie in scr3, and set bits re and te to 1 in scr3. setting bits te and re enables the txd 32 and rxd 32 pins to be used. in asynchronous mode the mark state is established when transmitting, and the idle state waiting for a start bit when receiving. 1. 2. 3. 4. figure 10.5 example of sci3 initialization flowchart
rev. 4.00, 05/03, page 338 of 562 ? transmitting figure 10.6 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 2 3 write transmit data to tdr read bit tend in ssr set pdr = 0, pcr = 1 clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? no yes yes yes no break output? read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. (after the te bit is set to 1, one frame of 1s is output, then transmission is possible.) when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.6 example of data transmission flowchart (asynchronous mode)
rev. 4.00, 05/03, page 339 of 562 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd 32 pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1, bit tend in ssr bit is set to 1the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.7 shows an example of the operation when transmitting in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.7 example of operation when transmitting in asynchronous mode (8-bit data, parity, 1 stop bit)
rev. 4.00, 05/03, page 340 of 562 ? receiving figure 10.8 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bits oer, per, fer in ssr 1 2 3 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + per + fer = 1? no rdrf = 1? yes continue data reception? no no yes receive error processing (a) read bits oer, per, and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the stop bit of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. 1. 2. 3. figure 10.8 example of data reception flowchart (asynchronous mode)
rev. 4.00, 05/03, page 341 of 562 start receive error processing end of receive error processing 4 clear bits oer, per, fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? yes per = 1? no no no no overrun error processing framing error processing (a) parity error processing if a receive error has occurred, read bits oer, per, and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer, per, and fer are all cleared to 0. reception cannot be resumed if any of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 32 pin. 4. figure 10.8 example of data reception flowchart (asynchronous mode) (cont)
rev. 4.00, 05/03, page 342 of 562 sci3 operates as follows when receiving data. sci3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. reception is carried out in accordance with the relevant data transfer format in table 10.11. the received data is first placed in rsr in lsb-to-msb order, and then the parity bit and stop bit(s) are received. sci3 then carries out the following checks. ? parity check sci3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit pm in the serial mode register (smr). ? stop bit check sci3 checks that the stop bit is 1. if two stop bits are used, only the first is checked. ? status check sci3 checks that bit rdrf is set to 0, indicating that the receive data can be transferred from rsr to rdr. if no receive error is found in the above checks, bit rdrf is set to 1, and the receive data is stored in rdr. if bit rie is set to 1 in scr3, an rxi interrupt is requested. if the error checks identify a receive error, bit oer, per, or fer is set to 1 depending on the kind of error. bit rdrf retains its state prior to receiving the data. if bit rie is set to 1 in scr3, an eri interrupt is requested. table 10.12 shows the conditions for detecting a receive error, and receive data processing. note: no further receive operations are possible while a receive error flag is set. bits oer, fer, per, and rdrf must therefore be cleared to 0 before resuming reception. table 10.12 receive error detection conditions and receive data processing receive error abbr. detection conditions receive data processing overrun error oer when the next date receive operation is completed while bit rdrf is still set to 1 in ssr receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the parity (odd or even) set in smr is different from that of the received data receive data is transferred from rsr to rdr
rev. 4.00, 05/03, page 343 of 562 figure 10.9 shows an example of the operation when receiving in asynchronous mode. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1 d0 d1 d7 0/1 1 0 1 0 d0 d1 d7 0/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 start bit detected eri request in response to framing error figure 10.9 example of operation when receiving in asynchronous mode (8-bit data, parity, 1 stop bit) 10.3.3 operation in synchronous mode in synchronous mode, sci3 transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. sci3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. as the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception.
rev. 4.00, 05/03, page 344 of 562 1. data transfer format the general data transfer format in asynchronous communication is shown in figure 10.10. serial clock serial data note: * high level except in continuous transmission/reception lsb msb * * bit 1 bit 0 bit 2 bit 3 bit 4 8 bits one transfer data unit (character or frame) bit 5 bit 6 bit 7 dont care dont care figure 10.10 data format in synchronous communication in synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. data confirmation is guaranteed at the rising edge of the serial clock. one transfer data character begins with the lsb and ends with the msb. after output of the msb, the communication line retains the msb state. when receiving in synchronous mode, sci3 latches receive data at the rising edge of the serial clock. the data transfer format uses a fixed 8-bit data length. parity and multiprocessor bits cannot be added. 2. clock either an internal clock generated by the baud rate generator or an external clock input at the sck 32 pin can be selected as the sci3 serial clock. the selection is made by means of bit com in smr and bits cke1 and cke0 in scr3. see table 10.9 for details on clock source selection. when sci3 operates on an internal clock, the serial clock is output at the sck 32 pin. eight pulses of the serial clock are output in transmission or reception of one character, and when sci3 is not transmitting or receiving, the clock is fixed at the high level.
rev. 4.00, 05/03, page 345 of 562 3. data transfer operations ? sci3 initialization data transfer on sci3 first of all requires that sci3 be initialized as described in section 10.3.2, 3. sci3 initialization, and shown in figure 10.5. ? transmitting figure 10.11 shows an example of a flowchart for data transmission. this procedure should be followed for data transmission after initializing sci3. start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 2 write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 no tdre = 1? yes continue data transmission? no tend = 1? yes yes no read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically, the clock is output, and data transmission is started. when clock output is selected, the clock is output and data transmission started when data is written to tdr. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. 1. 2. figure 10.11 example of data transmission flowchart (synchronous mode)
rev. 4.00, 05/03, page 346 of 562 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. when clock output mode is selected, sci3 outputs 8 serial clock pulses. when an external clock is selected, data is output in synchronization with the input clock. serial data is transmitted from the txd32 pin in order from the lsb (bit 0) to the msb (bit 7). when the msb (bit 7) is sent, checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and starts transmission of the next frame. if bit tdre is set to 1, sci3 sets bit tend to 1 in ssr, and after sending the msb (bit 7), retains the msb state. if bit teie in scr3 is set to 1 at this time, a tei request is made. after transmission ends, the sck pin is fixed at the high level. note: transmission is not possible if an error flag (oer, fer, or per) that indicates the data reception status is set to 1. check that these error flags are all cleared to 0 before a transmit operation. figure 10.12 shows an example of the operation when transmitting in synchronous mode. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi request data written to tdr tdre cleared to 0 txi request tei request figure 10.12 example of operation when transmitting in synchronous mode
rev. 4.00, 05/03, page 347 of 562 ? receiving figure 10.13 shows an example of a flowchart for data reception. this procedure should be followed for data reception after initializing sci3. start end read bit oer in ssr 1 2 3 4 read bit rdrf in ssr overrun error processing 4 clear bit oer to 0 in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer = 1? no rdrf = 1? yes continue data reception? no no yes overrun error processing end of overrun error processing start overrun error processing read bit oer in the serial status register (ssr) to determine if there is an error. if an overrun error has occurred, execute overrun error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. reception cannot be resumed if bit oer is set to 1. 1. 2. 3. 4. figure 10.13 example of data reception flowchart (synchronous mode)
rev. 4.00, 05/03, page 348 of 562 sci3 operates as follows when receiving data. sci3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. the received data is placed in rsr in lsb-to-msb order. after the data has been received, sci3 checks that bit rdrf is set to 0, indicating that the receive data can be transferred from rsr to rdr. if this check shows that there is no overrun error, bit rdrf is set to 1, and the receive data is stored in rdr. if bit rie is set to 1 in scr3, an rxi interrupt is requested. if the check identifies an overrun error, bit oer is set to 1. bit rdrf remains set to 1. if bit rie is set to 1 in scr3, an eri interrupt is requested. see table 10.12 for the conditions for detecting a receive error, and receive data processing. note: no further receive operations are possible while a receive error flag is set. bits oer, fer, per, and rdrf must therefore be cleared to 0 before resuming reception. figure 10.14 shows an example of the operation when receiving in synchronous mode. serial clock serial data bit 0 bit 7 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi request rdr data read rdre cleared to 0 rxi request eri request in response to overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 10.14 example of operation when receiving in synchronous mode
rev. 4.00, 05/03, page 349 of 562 ? simultaneous transmit/receive figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. this procedure should be followed for simultaneous transmission/reception after initializing sci3. start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 2 3 4 write transmit data to tdr read bit oer in ssr read bit rdrf in ssr clear bits te and re to 0 in scr3 yes tdre = 1? no oer = 1? no rdrf = 1? yes continue data transmission/reception? no yes no read receive data in rdr yes overrun error processing read the serial status register (ssr) and check that bit tdre is set to 1, then write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr. when the rdr data is read, bit rdrf is cleared to 0 automatically. when continuing data transmission/reception, finish reading of bit rdrf and rdr before receiving the msb (bit 7) of the current frame. before receiving the msb (bit 7) of the current frame, also read tdre = 1 to confirm that a write can be performed, then write data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically, and when the data in rdr is read, bit rdrf is cleared to 0 automatically. if an overrun error has occurred, read bit oer in ssr, and after carrying out the necessary error processing, clear bit oer to 0. transmis- sion and reception cannot be resumed if bit oer is set to 1. see figure 10.13 for details on overrun error processing. 1. 2. 3. 4. figure 10.15 example of simultaneous data transmission/reception flowchart (synchronous mode)
rev. 4.00, 05/03, page 350 of 562 notes: 1. when switching from transmission to simultaneous transmission/reception, check that sci3 has finished transmitting and that bits tdre and tend are set to 1, clear bit te to 0, and then set bits te and re to 1 simultaneously. 2. when switching from reception to simultaneous transmission/reception, check that sci3 has finished receiving, clear bit re to 0, then check that bit rdrf and the error flags (oer, fer, and per) are cleared to 0, and finally set bits te and re to 1 simultaneously. 10.3.4 multiprocessor communication function the multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). in multiprocessor communication, each receiver is assigned its own id code. the serial communication cycle consists of two cycles, an id transmission cycle in which the receiver is specified, and a data transmission cycle in which the transfer data is sent to the specified receiver. these two cycles are differentiated by means of the multiprocessor bit, 1 indicating an id transmission cycle, and 0, a data transmission cycle. the sender first sends transfer data with a 1 multiprocessor bit added to the id code of the receiver it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the transmit data. when a receiver receives transfer data with the multiprocessor bit set to 1, it compares the id code with its own id code, and if they are the same, receives the transfer data sent next. if the id codes do not match, it skips the transfer data until data with the multiprocessor bit set to 1 is sent again. in this way, a number of processors can exchange data among themselves. figure 10.16 shows an example of communication between processors using the multiprocessor format.
rev. 4.00, 05/03, page 351 of 562 sender serial data receiver a (id = 01) (id = 02) receiver b h01 id transmission cycle (specifying the receiver) data transmission cycle (sending data to the receiver specified by the id) mpb: multiprocessor bit (mpb = 1) (mpb = 0) haa communication line (id = 03) receiver c (id = 04) receiver d figure 10.16 example of inter-processor communication using multiprocessor format (sending data h'aa to receiver a) there is a choice of four data transfer formats. if a multiprocessor format is specified, the parity bit specification is invalid. see table 10.11 for details. for details on the clock used in multiprocessor communication, see section 10.3.2, operation in asynchronous mode. ? multiprocessor transmitting figure 10.17 shows an example of a flowchart for multiprocessor data transmission. this procedure should be followed for multiprocessor data transmission after initializing sci3.
rev. 4.00, 05/03, page 352 of 562 start end read bit tdre in ssr sets bit spc32 to 1 in spcr 1 3 2 set bit mpbt in ssr write transmit data to tdr read bit tend in ssr clear bit te to 0 in scr3 set pdr = 0, pcr = 1 yes tdre = 1? no continue data transmission? no tend = 1? break output? no yes yes no yes read the serial status register (ssr) and check that bit tdre is set to 1, then set bit mpbt in ssr to 0 or 1 and write transmit data to the transmit data register (tdr). when data is written to tdr, bit tdre is cleared to 0 automatically. when continuing data transmission, be sure to read tdre = 1 to confirm that a write can be performed before writing data to tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. if a break is to be output when data transmission ends, set the port pcr to 1 and clear the port pdr to 0, then clear bit te in scr3 to 0. 1. 2. 3. figure 10.17 example of multiprocessor data transmission flowchart
rev. 4.00, 05/03, page 353 of 562 sci3 operates as follows when transmitting data. sci3 monitors bit tdre in ssr, and when it is cleared to 0, recognizes that data has been written to tdr and transfers data from tdr to tsr. it then sets bit tdre to 1 and starts transmitting. if bit tie in scr3 is set to 1 at this time, a txi request is made. serial data is transmitted from the txd pin using the relevant data transfer format in table 10.11. when the stop bit is sent, sci3 checks bit tdre. if bit tdre is cleared to 0, sci3 transfers data from tdr to tsr, and when the stop bit has been sent, starts transmission of the next frame. if bit tdre is set to 1 bit tend in ssr bit is set to 1, the mark state, in which 1s are transmitted, is established after the stop bit has been sent. if bit teie in scr3 is set to 1 at this time, a tei request is made. figure 10.18 shows an example of the operation when transmitting using the multiprocessor format. 1 frame start bit start bit transmit data transmit data mpb mpb stop bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi request tdre cleared to 0 user processing data written to tdr txi request tei request figure 10.18 example of operation when transmitting using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit) ? multiprocessor receiving figure 10.19 shows an example of a flowchart for multiprocessor data reception. this procedure should be followed for multiprocessor data reception after initializing sci3.
rev. 4.00, 05/03, page 354 of 562 start end read bits oer and fer in ssr 2 set bit mpie to 1 in scr3 1 3 4 5 4 read bit rdrf in ssr read receive data in rdr clear bit re to 0 in scr3 yes oer + fer = 1? no rdrf = 1? yes continue data reception? no no yes read bits oer and fer in ssr no own id? yes read bit rdrf in ssr yes oer + fer = 1? no read receive data in rdr no rdrf = 1? yes receive error processing (a) set bit mpie to 1 in scr3. read bits oer and fer in the serial status register (ssr) to determine if there is an error. if a receive error has occurred, execute receive error processing. read ssr and check that bit rdrf is set to 1. if it is, read the receive data in rdr and compare it with this receivers own id. if the id is not this receivers, set bit mpie to 1 again. when the rdr data is read, bit rdrf is cleared to 0 automatically. read ssr and check that bit rdrf is set to 1, then read the data in rdr. if a receive error has occurred, read bits oer and fer in ssr to identify the error, and after carrying out the necessary error processing, ensure that bits oer and fer are both cleared to 0. reception cannot be resumed if either of these bits is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd 32 pin. 1. 2. 3. 4. 5. figure 10.19 example of multiprocessor data reception flowchart
rev. 4.00, 05/03, page 355 of 562 start receive error processing end of receive error processing clear bits oer and fer to 0 in ssr yes oer = 1? yes yes fer = 1? break? no no no overrun error processing framing error processing (a) figure 10.19 example of multiprocessor data reception flowchart (cont) figure 10.20 shows an example of the operation when receiving using the multiprocessor format.
rev. 4.00, 05/03, page 356 of 562 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 no rxi request rdr retains previous state rdr data read when data is not this receivers id, bit mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receivers id (b) when data matches this receivers id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi request mpie cleared to 0 user processing rdrf cleared to 0 rxi request rdrf cleared to 0 rdr data read when data is this receivers id, reception is continued rdr data read bit mpie set to 1 again figure 10.20 example of operation when receiving using multiprocessor format (8-bit data, multiprocessor bit, 1 stop bit)
rev. 4.00, 05/03, page 357 of 562 10.4 interrupts sci3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). these interrupts have the same vector address. the various interrupt requests are shown in table 10.13. table 10.13 sci3 interrupt requests interrupt abbr. interrupt request vector address rxi interrupt request initiated by receive data full flag (rdrf) h'0024 txi interrupt request initiated by transmit data empty flag (tdre) tei interrupt request initiated by transmit end flag (tend) eri interrupt request initiated by receive error flag (oer, fer, per) each interrupt request can be enabled or disabled by means of bits tie and rie in scr3. when bit tdre is set to 1 in ssr, a txi interrupt is requested. when bit tend is set to 1 in ssr, a tei interrupt is requested. these two interrupts are generated during transmission. the initial value of bit tdre in ssr is 1. therefore, if the transmit data empty interrupt request (txi) is enabled by setting bit tie to 1 in scr3 before transmit data is transferred to tdr, a txi interrupt will be requested even if the transmit data is not ready. also, the initial value of bit tend in ssr is 1. therefore, if the transmit end interrupt request (tei) is enabled by setting bit teie to 1 in scr3 before transmit data is transferred to tdr, a tei interrupt will be requested even if the transmit data has not been sent. effective use of these interrupt requests can be made by having processing that transfers transmit data to tdr carried out in the interrupt service routine. to prevent the generation of these interrupt requests (txi and tei), on the other hand, the enable bits for these interrupt requests (bits tie and teie) should be set to 1 after transmit data has been transferred to tdr. when bit rdrf is set to 1 in ssr, an rxi interrupt is requested, and if any of bits oer, per, and fer is set to 1, an eri interrupt is requested. these two interrupt requests are generated during reception. for further details, see section 3.3, interrupts.
rev. 4.00, 05/03, page 358 of 562 10.5 application notes the following points should be noted when using sci3. 1. relation between writes to tdr and bit tdre bit tdre in the serial status register (ssr) is a status flag that indicates that data for serial transmission has not been prepared in tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. when sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr irrespective of the state of bit tdre, but if new data is written to tdr while bit tdre is cleared to 0, the data previously stored in tdr will be lost of it has not yet been transferred to tsr. accordingly, to ensure that serial transmission is performed dependably, you should first check that bit tdre is set to 1, then write the transmit data to tdr once only (not two or more times). 2. operation when a number of receive errors occur simultaneously if a number of receive errors are detected simultaneously, the status flags in ssr will be set to the states shown in table 10.14. if an overrun error is detected, data transfer from rsr to rdr will not be performed, and the receive data will be lost. table 10.14 ssr status flag states and receive data transfer ssr status flags rdrf * oer fer per receive data transfer rsr rdr receive error status 1 100x overrun error 0 010o framing error 0 001o parity error 1 110x overrun error + framing error 1 101x overrun error + parity error 0 011o framing error + parity error 1 111x overrun error + framing error + parity error o : receive data is transferred from rsr to rdr. x : receive data is not transferred from rsr to rdr. note: * bit rdrf retains its state prior to data reception. however, note that if rdr is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, rdrf will be cleared to 0.
rev. 4.00, 05/03, page 359 of 562 3. break detection and processing when a framing error is detected, a break can be detected by reading the value of the rxd 32 pin directly. in a break, the input from the rxd 32 pin becomes all 0s, with the result that bit fer is set and bit per may also be set. sci3 continues the receive operation even after receiving a break. note, therefore, that even though bit fer is cleared to 0 it will be set to 1 again. 4. mark state and break detection when bit te is cleared to 0, the txd 32 pin functions as an i/o port whose input/output direction and level are determined by pdr and pcr. this fact can be used to set the txd 32 pin to the mark state, or to detect a break during transmission. to keep the communication line in the mark state (1 state) until bit te is set to 1, set pcr = 1 and pdr = 1. since bit te is cleared to 0 at this time, the txd 32 pin functions as an i/o port and 1 is output. to detect a break, clear bit te to 0 after setting pcr = 1 and pdr = 0. when bit te is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the txd 32 pin functions as an i/o port, and 0 is output from the txd 32 pin. 5. receive error flags and transmit operation (synchronous mode only) when a receive error flag (oer, per, or fer) is set to 1, transmission cannot be started even if bit tdre is cleared to 0. the receive error flags must be cleared to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if bit re is cleared to 0. 6. receive data sampling timing and receive margin in asynchronous mode in asynchronous mode, sci3 operates on a basic clock with a frequency 16 times the transfer rate. when receiving, sci3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. receive data is latched internally at the 8th rising edge of the basic clock. this is illustrated in figure 10.21.
rev. 4.00, 05/03, page 360 of 562 0 7 15 0 7 15 0 internal basic clock receive data (rxd32) start bit d0 16 clock pulses 8 clock pulses d1 synchronization sampling timing data sampling timing figure 10.21 receive data sampling timing in asynchronous mode consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). 1 d C 0.5 m ={(0.5 C 2n ) C n C (l C 0.5) f} 100 [%] ..... equation (1) where m: receive margin (%) n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock frequency deviation substituting 0 for f (absolute value of clock frequency deviation) and 0.5 for d (clock duty) in equation (1), a receive margin of 46.875% is given by equation (2). when d = 0.5 and f = 0, m = {0.5 C 1/(2 16)} 100 [%] = 46.875% .... equation (2) however, this is only a computed value, and a margin of 20% to 30% should be allowed when carrying out system design.
rev. 4.00, 05/03, page 361 of 562 7. relation between rdr reads and bit rdrf in a receive operation, sci3 continually checks the rdrf flag. if bit rdrf is cleared to 0 when reception of one frame ends, normal data reception is completed. if bit rdrf is set to 1, this indicates that an overrun error has occurred. when the contents of rdr are read, bit rdrf is cleared to 0 automatically. therefore, if bit rdr is read more than once, the second and subsequent read operations will be performed while bit rdrf is cleared to 0. note that, when an rdr read is performed while bit rdrf is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. this is illustrated in figure 10.22. communication line rdrf rdr frame 1 frame 2 frame 3 data 1 data 1 rdr read rdr read data 1 is read at point (a) data 2 data 3 data 2 (a) data 2 is read at point (b) (b) figure 10.22 relation between rdr read timing and data in this case, only a single rdr read operation (not two or more) should be performed after first checking that bit rdrf is set to 1. if two or more reads are performed, the data read the first time should be transferred to ram, etc., and the ram contents used. also, ensure that there is sufficient margin in an rdr read operation before reception of the next frame is completed. to be precise in terms of timing, the rdr read should be completed before bit 7 is transferred in synchronous mode, or before the stop bit is transferred in asynchronous mode. 8. transmit and receive operations when making a state transition make sure that transmit and receive operations have completely finished before carrying out state transition processing.
rev. 4.00, 05/03, page 362 of 562 9. switching sck 32 function if pin sck 32 is used as a clock output pin by sci3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock ( ) cycle immediately after it is switched. this can be prevented by either of the following methods according to the situation. a. when an sck 32 function is switched from clock output to non clock-output when stopping data transfer, issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. in this case, bit com in smr should be left 1. the above prevents sck 32 from being used as a general input/output pin. to avoid an intermediate level of voltage from being applied to sck 32 , the line connected to sck 32 should be pulled up to the v cc level via a resistor, or supplied with output from an external device. b. when an sck 32 function is switched from clock output to general input/output when stopping data transfer, (i) issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. (ii) clear bit com in smr to 0 (iii) clear bits cke1 and cke0 in scr3 to 0 note that special care is also needed here to avoid an intermediate level of voltage from being applied to sck 32 . 10. set up at subactive or subsleep mode at subactive or subsleep mode, sci3 becomes possible use only at cpu clock is w/2.
rev. 4.00, 05/03, page 363 of 562 section 11 10-bit pwm 11.1 overview the h8/38024 group is provided with two on-chip 10-bit pwms (pulse width modulators), designated pwm1 and pwm2, with identical functions. the pwms can be used as d/a converters by connecting a low-pass filter. in this section the suffix m (m = 1 or 2) is used with register names, etc., as in pwdrlm, which denotes the pwdrl registers for each pwm. 11.1.1 features features of the 10-bit pwms are as follows. ? choice of four conversion periods any of the following conversion periods can be chosen: 4,096/ , with a minimum modulation width of 4/ 2,048/ , with a minimum modulation width of 2/ 1,024/ , with a minimum modulation width of 1/ 512/ , with a minimum modulation width of 1/2 ? pulse division method for less ripple ? use of module standby mode enables this module to be placed in standby mode independently when not used.
rev. 4.00, 05/03, page 364 of 562 11.1.2 block diagram figure 11.1 shows a block diagram of the 10-bit pwm. internal data bus pwdrlm pwdrum pwcrm pwm waveform generator /2 /4 /8 notation: pwdrlm: pwdrum: pwcrm: pwm data register l pwm data register u pwm control register m = 1 or 2 pwmm figure 11.1 block diagram of the 10-bit pwm 11.1.3pin configuration table 11.1 shows the output pin assigned to the 10-bit pwm. table 11.1 pin configuration name abbr. i/o function pwm1 output pin pwm1 output pulse-division pwm waveform output (pwm1) pwm2 output pin pwm2 output pulse-division pwm waveform output (pwm2)
rev. 4.00, 05/03, page 365 of 562 11.1.4 register configuration table 11.2 shows the register configuration of the 10-bit pwm. table 11.2 register configuration name abbr. r/w initial value address pwm1 control register pwcr1 w h'fc h'ffd0 pwm1 data register u pwdru1 w h'fc h'ffd1 pwm1 data register l pwdrl1 w h'00 h'ffd2 pwm2 control register pwcr2 w h'fc h'ffcd pwm2 data register u pwdru2 w h'fc h'ffce pwm2 data register l pwdrl2 w h'00 h'ffcf clock stop register 2 ckstpr2 r/w h'ff h'fffb
rev. 4.00, 05/03, page 366 of 562 11.2 register descriptions 11.2.1 pwm control register (pwcrm) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcrm0 0 w 2 1 1 pwcrm1 0 w pwcrm is an 8-bit write-only register for input clock selection. upon reset, pwcrm is initialized to h'fc. bits 7 to 2: reserved bits bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. bits 1 and 0: clock select 1 and 0 (pwcrm1, pwcrm0) bits 1 and 0 select the clock supplied to the 10-bit pwm. these bits are write-only bits; they are always read as 1. bit 1 pwcrm1 bit 0 pwcrm0 description 0 0 the input clock is (t * = 1/ ) (initial value) the conversion period is 512/ , with a minimum modulation width of 1/2 0 1 the input clock is /2 (t * = 2/ ) the conversion period is 1,024/ , with a minimum modulation width of 1/ 1 0 the input clock is /4 (t * = 4/ ) the conversion period is 2,048/ , with a minimum modulation width of 2/ 1 1 the input clock is /8 (t * = 8/ ) the conversion period is 4,096/ , with a minimum modulation width of 4/ note: * period of pwm input clock.
rev. 4.00, 05/03, page 367 of 562 11.2.2 pwm data registers u and l (pwdrum, pwdrlm) bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwdrum0 0 w 2 1 1 pwdrum 1 0 w pwdrum bit initial value read/write 7 pwdrlm7 0 w 6 pwdrlm6 0 w 5 pwdrlm5 0 w 4 pwdrlm4 0 w 3 pwdrlm3 0 w 0 pwdrlm0 0 w 2 pwdrlm2 0 w 1 pwdrlm1 0 w pwdrlm pwdrum and pwdrlm form a 10-bit write-only register, with the upper 2 bits assigned to pwdrum and the lower 8 bits to pwdrlm. the value written to pwdrum and pwdrlm gives the total high-level width of one pwm waveform cycle. when 10-bit data is written to pwdrum and pwdrlm, the register contents are latched in the pwm waveform generator, updating the pwm waveform generation data. the 10-bit data should always be written in the following sequence: 1. write the lower 8 bits to pwdrlm. 2. write the upper 2 bits to pwdrum for the same channel. pwdrum and pwdrlm are write-only registers. if they are read, all bits are read as 1. upon reset, pwdrum is initialized to h'fc, and pwdrlm to h'00. 11.2.3clock stop register 2 (ckstpr2) wdckstp pw1ckstp ldckstp pw2ckstp aeckstp 76543210 1 1111111 r/w r/w r/w r/w r/w bit initial value read/write ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the pwm is described here. for details of the other bits, see the sections on the relevant modules.
rev. 4.00, 05/03, page 368 of 562 bits 4 and 1: pwm module standby mode control (pwmckstp) bits 4 and 1 control setting and clearing of module standby mode for the pwmm. pwmckstp description 0 pwmm is set to module standby mode 1 pwmm module standby mode is cleared (initial value)
rev. 4.00, 05/03, page 369 of 562 11.3operation 11.3.1 operation when using the 10-bit pwm, set the registers in the following sequence. 1. set pwm1 or pwm2 in pmr9 to 1 for the pwm channel to be used, so that pin p9 0 /pwm1 or p9 1 /pwm2 is designated as the pwm output pin. 2. set bits pwcrm1 and pwcrm0 in the pwm control register (pwcrm) to select a conversion period of 4,096/ (pwcrm1 = 1, pwcrm0 = 1), 2,048/ (pwcrm1 = 1, pwcrm0 = 0), 1,024/ (pwcrm1 = 0, pwcrm0 = 1), or 512/ (pwcrm1 = 0, pwcrm0 = 0). 3. set the output waveform data in pwdrum and pwdrlm. be sure to write in the correct sequence, first pwdrlm then pwdrum for the same channel. when data is written to pwdrum, the data will be latched in the pwm waveform generator, updating the pwm waveform generation in synchronization with internal signals. one conversion period consists of 4 pulses, as shown in figure 11.2. the total of the high-level pulse widths during this period (t h ) corresponds to the data in pwdrum and pwdrlm. this relation can be represented as follows. t h = (data value in pwdrum and pwdrlm + 4) t /2 where t is the pwm input clock period: 1/ (pwcrm = h'0), 2/ (pwcrm = h'1), 4/ (pwcrm = h'2), or 8/ (pwcrm = h'3). example: settings in order to obtain a conversion period of 1,024 s: when pwcrm1 = 0 and pwcrm0 = 0, the conversion period is 512/ , so must be 0.5 mhz. in this case, tfn = 256 s, with 1/2 (resolution) = 1.0 s. when pwcrm1 = 0 and pwcrm0 = 1, the conversion period is 1,024/ , so must be 1 mhz. in this case, tfn = 256 s, with 1/ (resolution) = 1.0 s. when pwcrm1 = 1 and pwcrm0 = 0, the conversion period is 2,048/ , so must be 2 mhz. in this case, tfn = 256 s, with 2/ (resolution) = 1.0 s. when pwcrm1 = 1 and pwcrm0 = 1, the conversion period is 4,096/ , so must be 4 mhz. in this case, t fn = 256 s, with 4/ (resolution) = 1.0 s accordingly, for a conversion period of 1,024 s, the system clock frequency ( ) must be 0.5 mhz, 1 mhz, 2 mhz, or 4mhz.
rev. 4.00, 05/03, page 370 of 562 1 conversion period t f1 t h1 t h2 t h3 t h4 t f2 t f3 t f4 t h = t h1 + t h2 + t h3 + t h4 t f1 = t f2 = t f3 = t f4 figure 11.2 pwm output waveform 11.3.2 pwm operation modes pwm operation modes are shown in table 11.3. table 11.3pwm operation modes operation mode reset active sleepwatch sub- active sub- sleep standby module standby pwcrmreset functions functions retained retained retained retained retained pwdrumreset functions functions retained retained retained retained retained pwdrlmreset functions functions retained retained retained retained retained
rev. 4.00, 05/03, page 371 of 562 section 12 a/d converter 12.1 overview the h8/38024 group includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 8 channels of analog input. 12.1.1 features the a/d converter has the following features. ? 10-bit resolution ? eight input channels ? conversion time: approx. 12.4 s per channel (at 5 mhz operation) ? built-in sample-and-hold function ? interrupt requested on completion of a/d conversion ? a/d conversion can be started by external trigger input ? use of module standby mode enables this module to be placed in standby mode independently when not used.
rev. 4.00, 05/03, page 372 of 562 12.1.2 block diagram figure 12.1 shows a block diagram of the a/d converter. internal data bus amr adsr adrrh adrrl control logic com- parator an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 av av cc ss multiplexer reference voltage irrad av cc av ss notation: amr: adsr: adrr: irrad: a/d mode register a/d start register a/d result register a/d conversion end interrupt request flag figure 12.1 block diagram of the a/d converter
rev. 4.00, 05/03, page 373 of 562 12.1.3 pin configuration table 12.1 shows the a/d converter pin configuration. table 12.1 pin configuration name abbr. i/o function analog power supply av cc input power supply and reference voltage of analog part analog ground av ss input ground and reference voltage of analog part analog input 0 an 0 input analog input channel 0 analog input 1 an 1 input analog input channel 1 analog input 2 an 2 input analog input channel 2 analog input 3 an 3 input analog input channel 3 analog input 4 an 4 input analog input channel 4 analog input 5 an 5 input analog input channel 5 analog input 6 an 6 input analog input channel 6 analog input 7 an 7 input analog input channel 7 external trigger input adtrg input external trigger input for starting a/d conversion 12.1.4 register configuration table 12.2 shows the a/d converter register configuration. table 12.2 register configuration name abbr. r/w initial value address a/d mode register amr r/w h'30 h'ffc6 a/d start register adsr r/w h'7f h'ffc7 a/d result register h adrrh r not fixed h'ffc4 a/d result register l adrrl r not fixed h'ffc5 clock stop register 1 ckstpr1 r/w h'ff h'fffa
rev. 4.00, 05/03, page 374 of 562 12.2 register descriptions 12.2.1 a/d result registers (adrrh, adrrl) bit 7 6 5 4 3 adrrh adrrl 0 21 76543 0 21 initial value read/write unde- fined r unde- fined r unde- fined r unde- fined r unde- fined r unde- fined r unde- fined r unde- fined r unde- fined r unde- fined r adr9 adr8 adr7 adr6 adr5 adr2 adr4 adr3 adr1 adr0 adrrh and adrrl together comprise a 16-bit read-only register for holding the results of analog-to-digital conversion. the upper 8 bits of the data are held in adrrh, and the lower 2 bits in adrrl. adrrh and adrrl can be read by the cpu at any time, but the adrrh and adrrl values during a/d conversion are not fixed. after a/d conversion is complete, the conversion result is stored as 10-bit data, and this data is held until the next conversion operation starts. adrrh and adrrl are not cleared on reset. 12.2.2 a/d mode register (amr) bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 5 1 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w amr is an 8-bit read/write register for specifying the a/d conversion speed, external trigger option, and the analog input pins. upon reset, amr is initialized to h'30.
rev. 4.00, 05/03, page 375 of 562 bit 7: clock select (cks) bit 7 sets the a/d conversion speed. conversion time bit 7 cks conversion period = 1 mhz = 5 mhz 0 62/ (initial value) 62 s 12.4 s 1 31/ 31 s * note: * operation is not guaranteed if the conversion time is less than 12.4 s. set bit 7 for a value of at least 12.4 s. bit 6: external trigger select (trge) bit 6 enables or disables the start of a/d conversion by external trigger input. bit 6 trge description 0 disables start of a/d conversion by external trigger (initial value) 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg * note: * the external trigger ( adtrg ) edge is selected by bit ieg4 of iegr. see 1. irq edge select register (iegr) in section 3.3.2 for details. bits 5 and 4: reserved bits bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. bits 3 to 0: channel select (ch3 to ch0) bits 3 to 0 select the analog input channel. the channel selection should be made while bit adsf is cleared to 0.
rev. 4.00, 05/03, page 376 of 562 bit 3 ch3 bit 2 ch2 bit 1 ch1 bit 0 ch0 analog input channel 00 ** no channel selected (initial value) 0 100an 0 0 101an 1 0 110an 2 0 111an 3 1 000an 4 1 001an 5 1 010an 6 1 011an 7 11 ** setting prohibited * : dont care 12.2.3 a/d start register (adsr) bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf) or by input of the designated edge of the external trigger signal, which also sets adsf to 1. when conversion is complete, the converted data is set in adrrh and adrrl, and at the same time adsf is cleared to 0. bit 7: a/d start flag (adsf) bit 7 controls and indicates the start and end of a/d conversion. bit 7 adsf description 0 read: indicates the completion of a/d conversion (initial value) write: stops a/d conversion 1 read: indicates a/d conversion in progress write: starts a/d conversion
rev. 4.00, 05/03, page 377 of 562 bits 6 to 0: reserved bits bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 12.2.4 clock stop register 1 (ckstpr1) tfckstp tcckstp tackstp s32ckstp adckstp tgckstp 76543210 1 1111111 r/w r/w r/w r/w r/w r/w bit initial value read/write ckstpr1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the a/d converter is described here. for details of the other bits, see the sections on the relevant modules. bit 4: a/d converter module standby mode control (adckstp) bit 4 controls setting and clearing of module standby mode for the a/d converter. adckstp description 0 a/d converter is set to module standby mode 1 a/d converter module standby mode is cleared (initial value)
rev. 4.00, 05/03, page 378 of 562 12.3 operation 12.3.1 a/d conversion operation the a/d converter operates by successive approximations, and yields its conversion result as 10- bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 2 (irr2) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 2 (ienr2) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 start of a/d conversion by external trigger input the a/d converter can be made to start a/d conversion by input of an external trigger signal. external trigger input is enabled at pin adtrg when bit irq4 in pmr1 is set to 1 and bit trge in amr is set to 1. then when the input signal edge designated in bit ieg4 of interrupt edge select register (iegr) is detected at pin adtrg , bit adsf in adsr will be set to 1, starting a/d conversion. figure 12.2 shows the timing. pin (when bit ieg4 = 0) adsf a/d conversion figure 12.2 external trigger input timing
rev. 4.00, 05/03, page 379 of 562 12.3.3 a/d converter operation modes a/d converter operation modes are shown in table 12.3. table 12.3 a/d converter operation modes operation mode reset active sleep watch sub- active sub- sleep standby module standby amr reset functions functions retained retained retained retained retained adsr reset functions functions retained retained retained retained retained adrrh retained * functions functions retained retained retained retained retained adrrl retained * functions functions retained retained retained retained retained note: * undefined in a power-on reset. 12.4 interrupts when a/d conversion ends (adsf changes from 1 to 0), bit irrad in interrupt request register 2 (irr2) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 2 (ienr2). for further details see section 3.3, interrupts. 12.5 typical use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 12.3 shows the operation timing. 1. bits ch3 to ch0 of the a/d mode register (amr) are set to 0101, making pin an 1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is complete, bit irrad is set to 1, and the a/d conversion result is stored in adrrh and adrrl. at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place.
rev. 4.00, 05/03, page 380 of 562 figures 12.4 and 12.5 show flow charts of procedures for using the a/d converter. idle a/d conversion (1) idle a/d conversion (2) idle interrupt (irrad) ienad adsf channel 1 (an 1 ) operation state adrrh adrrl set * set * set * read conversion result read conversion result a/d conversion result (1) a/d conversion result (2) a/d conversion starts note: * ( ) indicates instruction execution by software. figure 12.3 typical a/d converter operation timing
rev. 4.00, 05/03, page 381 of 562 start set a/d conversion speed and input channel perform a/d conversion? end yes no disable a/d conversion end interrupt start a/d conversion adsf = 0? no yes read adsr read adrrh/adrrl data figure 12.4 flow chart of procedure for using a/d converter (polling by software)
rev. 4.00, 05/03, page 382 of 562 start set a/d conversion speed and input channel enable a/d conversion end interrupt start a/d conversion a/d conversion end interrupt? yes no end yes no clear bit irrad to 0 in irr2 read adrrh/adrrl data perform a/d conversion? figure 12.5 flow chart of procedure for using a/d converter (interrupts used) 12.6 application notes 12.6.1 application notes ? data in adrrh and adrrl should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. ? changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. ? when a/d conversion is started after clearing module standby mode, wait for 10 clock cycles before starting. ? in active mode or sleep mode, analog power supply current (ai stop1 ) flows into the ladder resistance even when the a/d converter is not operating. therefore, if the a/d converter is not used, it is recommended that av cc be connected to the system power supply and the
rev. 4.00, 05/03, page 383 of 562 adckstp (a/d converter module standby mode control) bit be cleared to 0 in clock stop register 1 (ckstpr1). 12.6.2 permissible signal source impedance this lsis analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k ? or less. this specification is provided to enable the a/d converters sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversion precision. however, a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 12.6). when converting a high-speed analog signal, a low- impedance buffer should be inserted. 12.6.3 influences on absolute precision adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. a/d converter equivalent circuit this lsi 20 pf c in = 15 pf 10 k up to 10 k low-pass filter c to 0.1 f sensor output impedance sensor input figure 12.6 analog input circuit example
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rev. 4.00, 05/03, page 385 of 562 section 13 lcd controller/driver 13.1 overview the h8/38024 group has an on-chip segment type lcd control circuit, lcd driver, and power supply circuit, enabling it to directly drive an lcd panel. 13.1.1 features features of the lcd controller/driver are given below. ? display capacity duty cycle internal driver static 32 seg 1/2 32 seg 1/3 32 seg 1/4 32 seg ? lcd ram capacity 8 bits 16 bytes (128 bits) ? word access to lcd ram ? all four segment output pins can be used individually as port pins. ? common output pins not used because of the duty cycle can be used for common double- buffering (parallel connection). ? display possible in operating modes other than standby mode ? choice of 11 frame frequencies ? built-in power supply split-resistance, supplying lcd drive power ? use of module standby mode enables this module to be placed in standby mode independently when not used. ? a or b waveform selectable by software
rev. 4.00, 05/03, page 386 of 562 13.1.2 block diagram figure 13.1 shows a block diagram of the lcd controller/driver. /2 to /256 w seg n lpcr lcr lcr2 display timing generator lcd ram (16 bytes) internal data bus 32-bit shift register lcd drive power supply segment driver common data latch common driver v 1 v 2 v 3 v ss com 1 com 4 seg 32 seg 1 notation: lpcr: lcd port control register lcr: lcd control register lcr2: lcd control register 2 v cc figure 13.1 block diagram of lcd controller/driver
rev. 4.00, 05/03, page 387 of 562 13.1.3 pin configuration table 13.1 shows the lcd controller/driver pin configuration. table 13.1 pin configuration name abbr. i/o function segment output pins seg 32 to seg 1 output lcd segment drive pins all pins are multiplexed as port pins (setting programmable) common output pins com 4 to com 1 output lcd common drive pins pins can be used in parallel with static or 1/2 duty lcd power supply pins v 1 , v 2 , v 3 used when a bypass capacitor is connected externally, and when an external power supply circuit is used 13.1.4 register configuration table 13.2 shows the register configuration of the lcd controller/driver. table 13.2 lcd controller/driver registers name abbr. r/w initial value address lcd port control register lpcr r/w h'ffc0 lcd control register lcr r/w h'80 h'ffc1 lcd control register 2 lcr2 r/w h'ffc2 lcd ram r/w undefined h'f740 to h'f74f clock stop register 2 ckstpr2 r/w h'ff h'fffb
rev. 4.00, 05/03, page 388 of 562 13.2 register descriptions 13.2.1 lcd port control register (lpcr) bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 4 w 3 sgs3 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w lpcr is an 8-bit read/write register which selects the duty cycle and lcd driver pin functions. bits 7 to 5: duty cycle select 1 and 0 (dts1, dts0), common function select (cmx) the combination of dts1 and dts0 selects static, 1/2, 1/3, or 1/4 duty. cmx specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. bit 7 dts1 bit 6 dts0 bit 5 cmx duty cycle common drivers notes 000static com 1 (initial value) do not use com 4 , com 3 , and com 2 . 1com 4 to com 1 com 4 , com 3 , and com 2 output the same waveform as com 1 . 0101/2 dutycom 2 and com 1 do not use com 4 and com 3 . 1com 4 to com 1 com 4 outputs the same waveform as com 3 , and com 2 outputs the same waveform as com 1 . 1001/3 dutycom 3 to com 1 do not use com 4 . 1com 4 to com 1 do not use com 4 . 1101/4 dutycom 4 to com 1 1 bit 4: reserved bit bit 4 is reserved. it can only be written with 0. bits 3 to 0: segment driver select 3 to 0 (sgs3 to sgs0) bits 3 to 0 select the segment drivers to be used.
rev. 4.00, 05/03, page 389 of 562 function of pins seg 32 to seg 1 bit 3 sgs3 bit 2 sgs2 bit 1 sgs1 bit 0 sgs0 seg 32 to seg 29 seg 28 to seg 25 seg 24 to seg 21 seg 20 to seg 17 seg 16 to seg 13 seg 12 to seg 9 seg 8 to seg 5 seg 4 to seg 1 notes 0 0 0 0 port port port port port port port port (initial value) 1 port port port port port port port seg 1 0 port port port port port port seg seg 1 port port port port port seg seg seg 1 0 0 port port port port seg seg seg seg 1 port port port seg seg seg seg seg 1 0 port port seg seg seg seg seg seg 1 port seg seg seg seg seg seg seg 1 0 0 0 seg seg seg seg seg seg seg seg 1 seg seg seg seg seg seg seg port 1 0 seg seg seg seg seg seg port port 1 seg seg seg seg seg port port port 1 0 0 seg seg seg seg port port port port 1 seg seg seg port port port port port 10 seg seg port port port port port port 1 seg port port port port port port port
rev. 4.00, 05/03, page 390 of 562 13.2.2 lcd control register (lcr) bit initial value read/write 7 1 6 psw 0 r/w 5 act 0 r/w 4 disp 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w lcr is an 8-bit read/write register which performs lcd drive power supply on/off control and display data control, and selects the frame frequency. lcr is initialized to h'80 upon reset. bit 7: reserved bit bit 7 is reserved; it is always read as 1 and cannot be modified. bit 6: lcd drive power supply on/off control (psw) bit 6 can be used to turn the lcd drive power supply off when lcd display is not required in a power-down mode, or when an external power supply is used. when the act bit is cleared to 0, or in standby mode, the lcd drive power supply is turned off regardless of the setting of this bit. bit 6 psw description 0 lcd drive power supply off (initial value) 1 lcd drive power supply on bit 5: display function activate (act) bit 5 specifies whether or not the lcd controller/driver is used. clearing this bit to 0 halts operation of the lcd controller/driver. the lcd drive power supply is also turned off, regardless of the setting of the psw bit. however, register contents are retained. bit 5 actdescription 0 lcd controller/driver operation halted (initial value) 1 lcd controller/driver operates
rev. 4.00, 05/03, page 391 of 562 bit 4: display data control (disp) bit 4 specifies whether the lcd ram contents are displayed or blank data is displayed regardless of the lcd ram contents. bit 4 disp description 0 blank data is displayed (initial value) 1 lcd ram data is display bits 3 to 0: frame frequency select 3 to 0 (cks3 to cks0) bits 3 to 0 select the operating clock and the frame frequency. in subactive mode, watch mode, and subsleep mode, the system clock ( ) is halted, and therefore display operations are not performed if one of the clocks from /2 to /256 is selected. if lcd display is required in these modes, w, w/2, or w/4 must be selected as the operating clock. frame frequency * 2 bit 3 cks3 bit 2 cks2 bit 1 cks1 bit 0 cks0 operating clock = 2 mhz = 250 khz * 1 0 * 00 w 128 hz * 3 (initial value) 0 * 01 w/2 64 hz * 3 0 * 1 * w/4 32 hz * 3 1000 /2 244 hz 1001 /4 977 hz 122 hz 1010 /8 488 hz 61 hz 1011 /16 244 hz 30.5 hz 1100 /32 122 hz 1101 /64 61 hz 1110 /128 30.5 hz 1111 /256 * : dont care notes: * 1 this is the frame frequency in active (medium-speed, osc/16) mode when = 2 mhz. * 2 when 1/3 duty is selected, the frame frequency is 4/3 times the value shown. * 3 this is the frame frequency when w = 32.768 khz.
rev. 4.00, 05/03, page 392 of 562 13.2.3 lcd control register 2 (lcr2) bit initial value read/write 7 lcdab 0 r/w 6 1 5 1 4 w 3 w 0 w 2 w 1 w lcr2 is an 8-bit read/write register which controls switching between the a waveform and b waveform. bit 7: a waveform/b waveform switching control (lcdab) bit 7 specifies whether the a waveform or b waveform is used as the lcd drive waveform. bit 7 lcdab description 0 drive using a waveform (initial value) 1 drive using b waveform bits 6 and 5: reserved bits bits 6 and 5 are reserved; they are always read as 1 and cannot be modified. bits 4 to 0: reserved bits bits 4 to 0 are reserved; they can only be written with 0.
rev. 4.00, 05/03, page 393 of 562 13.2.4 clock stop register 2 (ckstpr2) bit initial value read/write 7 1 6 1 5 1 4 pw2ckstp 1 r/w 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 wdckstp 1 r/w 1 pw1ckstp 1 r/w ckstpr2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. only the bit relating to the lcd controller/driver is described here. for details of the other bits, see the sections on the relevant modules. bit 0: lcd controller/driver module standby mode control (ldckstp) bit 0 controls setting and clearing of module standby mode for the lcd controller/driver. bit 0 ldckstp description 0 lcd controller/driver is set to module standby mode 1 lcd controller/driver module standby mode is cleared (initial value)
rev. 4.00, 05/03, page 394 of 562 13.3 operation 13.3.1 settings up to lcd display to perform lcd display, the hardware and software related items described below must first be determined. 1. hardware settings a. using 1/2 duty when 1/2 duty is used, interconnect pins v 2 and v 3 as shown in figure 13.2. v cc v 1 v 2 v 3 v ss figure 13.2 handling of lcd drive power supply when using 1/2 duty b. large-panel display as the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a large panel. if the display lacks sharpness when using a large panel, refer to section 13.3.4, boosting the lcd drive power supply. when static or 1/2 duty is selected, the common output drive capability can be increased. set cmx to 1 when selecting the duty cycle. in this mode, with a static duty cycle pins com 4 to com 1 output the same waveform, and with 1/2 duty the com 1 waveform is output from pins com 2 and com 1 , and the com 2 waveform is output from pins com 4 and com 3 .
rev. 4.00, 05/03, page 395 of 562 2. software settings a. duty selection any of four duty cyclesstatic, 1/2 duty, 1/3 duty, or 1/4 dutycan be selected with bits dts1 and dts0. b. segment selection the segment drivers to be used can be selected with bits sgs 3 to sgs 0 . c. frame frequency selection the frame frequency can be selected by setting bits cks 3 to cks 0 . the frame frequency should be selected in accordance with the lcd panel specification. for the clock selection method in watch mode, subactive mode, and subsleep mode, see section 13.3.3, operation in power-down modes. d. a or b waveform selection either the a or b waveform can be selected as the lcd waveform to be used by means of lcdab.
rev. 4.00, 05/03, page 396 of 562 13.3.2 relationship between lcd ram and display the relationship between the lcd ram and the display segments differs according to the duty cycle. lcd ram maps for the different duty cycles are shown in figures 13.3 to 13.6. after setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary ram, and display is started automatically when turned on. word- or byte-access instructions can be used for ram setting. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg2 seg2 seg2 seg2 seg1 seg1 seg1 seg1 hf740 hf74f seg31 seg32 seg32 seg32 seg32 seg31 seg31 seg31 com4 com3 com2 com1 com4 com3 com2 com1 figure 13.3 lcd ram map (1/4 duty)
rev. 4.00, 05/03, page 397 of 562 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg2 seg2 seg2 seg1 seg1 seg1 hf740 hf74f seg31 seg32 seg32 seg32 seg31 seg31 com3 com2 com1 com3 com2 com1 space not used for display figure 13.4 lcd ram map (1/3 duty)
rev. 4.00, 05/03, page 398 of 562 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg4 seg4 seg3 seg3 seg2 seg2 seg1 seg1 hf740 hf747 hf74f seg29 seg30 seg30 seg31 seg31 seg32 seg32 seg29 com2 com1 com2 com1 com2 com1 com2 com1 display space space not used for display figure 13.5 lcd ram map (1/2 duty) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 hf740 hf743 hf74f seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 com1 com1 com1 com1 com1 com1 com1 com1 space not used for display display space figure 13.6 lcd ram map (static mode)
rev. 4.00, 05/03, page 399 of 562 1 frame m data com1 com2 com3 com4 segn v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty 1 frame m data com1 com2 com3 segn v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame m data com1 com2 segn v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss 1 frame m data com1 segn v 1 v ss v 1 v ss (b) waveform with 1/3 duty (c) waveform with 1/2 duty (d) waveform with static output m: lcd alternation signal figure 13.7 output waveforms for each duty cycle (a waveform)
rev. 4.00, 05/03, page 400 of 562 m data com1 com2 segn v 1 v 2, v 3 v ss v 1 v 2, v 3 v ss m data com1 segn v 1 v ss v 1 v ss (c) waveform with 1/2 duty m: lcd alternation signal (d) waveform with static output 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame (b) waveform with 1/3 duty m data com3 segn com1 v 1 v 2 v 3 v ss com2 v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss (a) waveform with 1/4 duty m data com1 com2 com3 com4 segn v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss v 1 v 2 v 3 v ss 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame v 1 v 2, v 3 v ss figure 13.8 output waveforms for each duty cycle (b waveform)
rev. 4.00, 05/03, page 401 of 562 table 13.3 output levels data 0011 m 0101 static common output v 1 v ss v 1 v ss segment output v 1 v ss v ss v 1 1/2 duty common output v 2 , v 3 v 2 , v 3 v 1 v ss segment output v 1 v ss v ss v 1 1/3 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 1/4 duty common output v 3 v 2 v 1 v ss segment output v 2 v 3 v ss v 1 m: lcd alternation signal 13.3.3 operation in power-down modes in the h8/38024 group, the lcd controller/driver can be operated even in the power-down modes. the operating state of the lcd controller/driver in the power-down modes is summarized in table 13.4. in subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless w, w/2, or w/4 has been selected by bits cks3 to cks0, the clock will not be supplied and display will halt. since there is a possibility that a direct current will be applied to the lcd panel in this case, it is essential to ensure that w, w/2, or w/4 is selected. in active (medium-speed) mode, the system clock is switched, and therefore cks3 to cks0 must be modified to ensure that the frame frequency does not change. table 13.4 power-down modes and display operation mode reset active sleep watch sub- active sub- sleep standby module standby clock runs runs runs stops stops stops stops stops * 4 w runs runs runs runs runs runs stops * 1 stops * 4 act = 0 stops stops stops stops stops stops stops * 2 stops display operation act = 1 stops functions functions functions * 3 functions * 3 functions * 3 stops * 2 stops notes: * 1 the subclock oscillator does not stop, but clock supply is halted. * 2 the lcd drive power supply is turned off regardless of the setting of the psw bit. * 3 display operation is performed only if w, w/2, or w/4 is selected as the operating clock. * 4 the clock supplied to the lcd stops.
rev. 4.00, 05/03, page 402 of 562 13.3.4 boosting the lcd drive power supply when a large panel is driven, the on-chip power supply capacity may be insufficient. if the power supply capacity is insufficient when v cc is used as the power supply, the power supply impedance must be reduced. this can be done by connecting bypass capacitors of around 0.1 to 0.3 f to pins v 1 to v 3 , as shown in figure 13.9, or by adding a split-resistance externally. h8/38024 group v cc v ss v 1 v 2 v 3 r r r r = several k to several m c = 0.1 to 0.3 f r figure 13.9 connection of external split-resistance
rev. 4.00, 05/03, page 403 of 562 section 14 electrical characteristics 14.1 h8/38024 ztat version and mask rom version absolute maximum ratings table 14.1 lists the absolute maximum ratings. table 14.1 absolute maximum ratings item symbol value unit note power supply voltage v cc C0.3 to +7.0 v * 1 analog power supply voltage av cc C0.3 to +7.0 v programming voltage v pp C0.3 to +13.0 v input voltage ports other than port b and irqaec v in C0.3 to v cc +0.3 v port b av in C0.3 to av cc +0.3 v irqaec hv in C0.3 to +7.3 v port 9 pin voltage v p9 C0.3 to +7.3 v operating temperature t opr C20 to +75 (regular specifications) c C40 to +85 (wide-range specifications) c storage temperature t stg C55 to +125 c notes: * 1permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability.
rev. 4.00, 05/03, page 404 of 562 14.2 h8/38024 ztat version and mask rom version electrical characteristics 14.2.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 1.8 3.0 5.5 v cc (v) f w (khz) ? all operating note 2: when an oscillator is used for the subclock, hold v cc at 2.2 v to 5.5 v from power-on until the oscillation settling time has elapsed. 32.768 4.5 16.0 2.0 10.0 4.0 1.8 2.7 4.5 5.5 v cc (v) fosc (mhz) ? active (high-speed) mode ? sleep (high-speed) mode note 1: the fosc values are those when an oscillator is used; when an external clock is used the minimum value of fosc is 1 mhz.
rev. 4.00, 05/03, page 405 of 562 2. power supply voltage and operating frequency range ? subactive mode ? subsleep mode (except cpu) ? watch mode (except cpu) 16.384 8.192 4.096 1.8 3.6 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 8.0 (0.5) 5.0 2.0 1.0 1.8 2.7 4.5 5.5 v cc (v) (mhz) 1000 (7.8125) 625 250 15.625 1.8 2.7 4.5 5.5 v cc (v) (khz) note 1: the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 1 mhz. note 2: the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 15.625 khz. ? active (high-speed) mode ? sleep (high-speed) mode (except cpu) ? active (medium-speed) mode ? sleep (medium-speed) mode (except a/d converter) 3. analog power supply voltage and a/d converter operating range (mhz) (0.5) 5.0 1.0 1.8 2.7 4.5 5.5 av cc (v) (khz) 500 1000 625 1.8 2.7 4.5 5.5 av cc (v) ? active (medium-speed) mode ? sleep (medium-speed) mode ? active (high-speed) mode ? sleep (high-speed) mode note 3: when av cc = 1.8 v to 2.7 v, the operating range is limited to = 1.0 mhz when using an oscillator, and is = 0.5 mhz to 1.0 mhz when using an external clock.
rev. 4.00, 05/03, page 406 of 562 14.2.2 dc characteristics table 14.2 lists the dc characteristics of the h8/38024. table 14.2 dc characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes v ih 0.8 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v input high voltage res , wkp 0 to wkp 7 , irq 0 , irq 1 , irq 3 , irq 4 , aevl, aevh, tmic, tmif, tmig, adtrg , sck 32 0.9 v cc v cc + 0.3 except the above rxd 32 , ud 0.7 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.8 v cc v cc + 0.3 except the above osc 1 0.8 v cc v cc + 0.3 v v cc = 4.0 v to 5.5 v 0.9 v cc v cc + 0.3 except the above x 1 0.9 v cc v cc + 0.3 v v cc = 1.8 v to 5.5 v 0.7 v cc v cc + 0.3 v cc = 4.0 v to 5.5 v p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.8 v cc v cc + 0.3 v except the above pb 0 to pb 7 0.7 v cc av cc + 0.3 v cc = 4.0 v to 5.5 v 0.8 v cc av cc + 0.3 except the above irqaec 0.8 v cc 7.3 vv cc = 4.0 v to 5.5 v 0.9 v cc 7.3 except the above
rev. 4.00, 05/03, page 407 of 562 values item symbol applicable pins min typ max unit test condition notes v il C0.3 0.2 v cc vv cc = 4.0 v to 5.5 v input low voltage res , wkp 0 to wkp 7 , irq 0 , irq 1 , irq 3 , irq 4 , irqaec, aevl, aevh, tmic, tmif, tmig, adtrg , sck 32 C0.3 0.1 v cc except the above rxd 32 , ud C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v C0.3 0.2 v cc except the above osc 1 C0.3 0.2 v cc vv cc = 4.0 v to 5.5 v C0.3 0.1 v cc except the above x 1 C0.3 0.1 v cc vv cc = 1.8 v to 5.5 v C0.3 0.3 v cc vv cc = 4.0 v to 5.5 v p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 C0.3 0.2 v cc except the above output high voltage v oh v cc C 1.0 v v cc = 4.0 v to 5.5 v Ci oh = 1.0 ma v cc C 0.5 v cc = 4.0 v to 5.5 v Ci oh = 0.5 ma p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc C 0.3 Ci oh = 0.1 ma
rev. 4.00, 05/03, page 408 of 562 values item symbol applicable pins min typ max unit test condition notes output low voltage v ol 0.6 vv cc = 4.0 v to 5.5 v i ol = 1.6 ma p1 3 , p1 4 , p1 6 , p1 7 , p4 0 to p4 2 0.5 i ol = 0.4 ma p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.5 i ol = 0.4 ma p3 0 to p3 7 1.5 v cc = 4.0 v to 5.5 v i ol = 10 ma 0.6 v cc = 4.0 v to 5.5 v i ol = 1.6 ma 0.5 i ol = 0.4 ma p9 0 to p9 2 0.5 v cc = 2.2 to 5.5 v i ol = 25 ma * 5 i ol = 15 ma 0.5 i ol = 10 ma * 6 p9 3 to p9 5 0.5 i ol = 10 ma | i il | res , p4 3 20.0 a * 2 1.0 v in = 0.5 v to v cc C 0.5 v * 1 input/output leakage current osc 1 , x 1 , p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , irqaec, p9 0 to p9 5 , pa 0 to pa 3 1.0 av in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 1.0 v in = 0.5 v to av cc C 0.5 v
rev. 4.00, 05/03, page 409 of 562 values item symbol applicable pins min typ max unit test condition notes pull-up mos current Ci p 50.0 300.0 a v cc = 5 v, v in = 0 v p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p5 0 to p5 7 , p6 0 to p6 7 35.0 v cc = 2.7 v, v in = 0 v reference value input capacitance c in all input pins except power supply, res , p4 3 , pb 0 to pb 7 15.0 pf f = 1 mhz, v in =0 v, t a = 25c irqaec 30.0 res 80.0 * 2 15.0 * 1 p4 3 50.0 * 2 15.0 * 1 pb 0 to pb 7 15.0 i ope1 v cc 7.0 10.0 ma active (high-speed) mode v cc = 5 v, f osc = 10 mhz * 3 * 4 active mode current dissipation i ope2 v cc 2.2 3.0 ma active (medium- speed) mode v cc = 5 v, f osc = 10 mhz osc /128 * 3 * 4 sleep mode current dissipation i sleep v cc 3.85.0 mav cc =5 v, f osc =10 mhz * 3 * 4 subactive mode current dissipation i sub v cc 15.0 30.0 a v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4 8.0 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /8) * 3 * 4 reference value subsleep mode current dissipation i subsp v cc 7.5 16.0 a v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4
rev. 4.00, 05/03, page 410 of 562 values item symbol applicable pins min typ max unit test condition notes watch mode current dissipation i watch v cc 3.86.0 av cc = 2.7 v, 32 khz crystal oscillator lcd not used * 2 * 3 * 4 2.8 6.0 * 1 * 3 * 4 standby mode current dissipation i stby v cc 1.0 5.0 a 32 khz crystal oscillator not used * 3 * 4 ram data retaining voltage v ram v cc 1.5 v i ol output pins except port 3 and 9 2.0 mav cc = 4.0 v to 5.5 v port 3 10.0 v cc = 4.0 v to 5.5 v allowable output low current (per pin) output pins except port 9 0.5 p9 0 to p9 2 25.0 v cc = 2.2 v to 5.5 v * 5 15.0 10.0 p9 3 to p9 5 10.0 i ol output pins except ports 3 and 9 40.0 ma v cc = 4.0 v to 5.5 v allowable output low current (total) port 3 80.0 v cc = 4.0 v to 5.5 v output pins except port 9 20.0 port 9 80.0 Ci oh all output pins 2.0 ma v cc = 4.0 v to 5.5 v allowable output high current (per pin) 0.2 except the above C i oh all output pins 15.0 ma v cc = 4.0 v to 5.5 v allowable output high current (total) 10.0 except the above
rev. 4.00, 05/03, page 411 of 562 notes: connect the test pin to v ss . * 1applies to the mask rom products. * 2 applies to the hd64738024. * 3 pin states during current measurement. mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc operates v cc halted active (medium- speed) mode (i ope2 ) sleep mode v cc only timers operate v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd subactive mode v cc operates v cc halted subsleep mode v cc only timers operate, cpu stops v cc halted watch mode v cc only time base operates, cpu stops v cc halted system clock oscillator: crystal subclock oscillator: crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd * 4 excludes current in pull-up mos transistors and output buffers. * 5 when the pioff bit in the port mode register 9 is 0. * 6 when the pioff bit in the port mode register 9 is 1.
rev. 4.00, 05/03, page 412 of 562 14.2.3 ac characteristics table 14.3 lists the control signal timing, and tables 14.4 lists the serial interface timing of the h8/38024. table 14.3 control signal timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition reference figure f osc osc 1 , osc 2 2.0 16.0 mhz v cc = 4.5 v to 5.5 v 2.0 10.0 v cc = 2.7 v to 5.5 v system clock oscillation frequency 2.0 4.0 except the above osc clock ( osc ) cycle time t osc osc 1 , osc 2 62.5 500 (1000) ns v cc = 4.5 v to 5.5 v figure 14.1 * 2 100 500 (1000) v cc = 2.7 v to 5.5 v 250 500 (1000) except the above t cyc 2 128 t osc system clock ( ) cycle time 128 s subclock oscillation frequency f w x 1 , x 2 32.768 or 38.4 khz watch clock ( w ) cycle time t w x 1 , x 2 30.5 or 26.0 s figure 14.1 subclock ( sub ) cycle time t subcyc 2 8 t w * 1 instruction cycle time 2 t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 20 45 s figure 14.8 v cc = 2.2 v to 5.5 v figure 14.8 50 ms except the above x 1 , x 2 2.0 s v cc = 2.7 v to 5.5 v * 3 10.0 v cc = 2.2 v to 5.5 v
rev. 4.00, 05/03, page 413 of 562 values item symbol applicable pins min typ max unit test condition reference figure t cph osc 1 25 ns v cc = 4.5 v to 5.5 v figure 14.1 external clock high width 40 v cc = 2.7 v to 5.5 v 100 except the above x 1 15.26 or 13.02 s t cpl osc 1 25 ns v cc = 4.5 v to 5.5 v figure 14.1 external clock low width 40 v cc = 2.7 v to 5.5 v 100 except the above x 1 15.26 or 13.02 s t cpr osc 1 6 ns v cc = 4.5 v to 5.5 v figure 14.1 external clock rise time 10 v cc = 2.7 v to 5.5 v 25 except the above x 1 55.0 ns t cpf osc 1 6 ns v cc = 4.5 v to 5.5 v figure 14.1 external clock fall time 10 v cc = 2.7 v to 5.5 v 25 except the above x 1 55.0 ns pin res low width t rel res 10 t cyc figure 14.2 input pin high width t ih irq 0 , irq 1 , irq 3 , irq 4 , irqaec, wkp 0 to wkp 7 , tmic, tmif, tmig, adtrg 2 t cyc t subcyc figure 14.3 aevl, aevh 0.5 t osc input pin low width t il irq 0 , irq 1 , irq 3 , irq 4 , irqaec, wkp 0 to wkp 7 , tmic, tmif, tmig, adtrg 2 t cyc t subcyc figure 14.3 aevl, aevh 0.5 t osc ud pin minimum transition width t udh t udl ud 4 t cyc t subcyc figure 14.6
rev. 4.00, 05/03, page 414 of 562 notes: * 1selected with sa1 and sa0 of system control register 2 (syscr2). * 2 the figure in parentheses applies when an external clock is used. * 3 after powering on, hold v cc at 2.2 v to 5.5 v until the chip's oscillation settling time has elapsed. table 14.4 serial interface (sci3) timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise indicated. values item symbol min typ max unit test conditions reference figure asynchronous t scyc 4 t cyc or figure 14.4 input clock cycle synchronous 6 t subcyc input clock pulse width t sckw 0.4 0.6 t scyc figure 14.4 t txd 1t cyc or v cc = 4.0 v to 5.5 v figure 14.5 transmit data delay time (synchronous) 1t subcyc except the above t rxs 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 receive data setup time (synchronous) 400.0 except the above figure 14.5 t rxh 200.0 ns v cc = 4.0 v to 5.5 v figure 14.5 receive data hold time (synchronous) 400.0 except the above figure 14.5
rev. 4.00, 05/03, page 415 of 562 14.2.4 a/d converter characteristics table 14.5 shows the a/d converter characteristics of the h8/38024. table 14.5 a/d converter characteristics v cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) unless otherwise indicated. values item symbol applicable pins min typ max unit test condition reference figure analog power supply voltage av cc av cc 1.8 5.5 v * 1 analog input voltage av in an 0 to an 7 C 0.3 av cc + 0.3 v ai ope av cc 1.5 maav cc = 5.0 v analog power supply current ai stop1 av cc 600 a * 2 reference value ai stop2 av cc 5 a * 3 analog input capacitance c ain an 0 to an 7 15.0 pf allowable signal source impedance r ain 10.0 k ? resolution (data length) 10 bit nonlinearity error 2.5 lsbav cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v 5.5 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v 7.5 except the above * 4 quantization error 0.5 lsb
rev. 4.00, 05/03, page 416 of 562 values item symbol applicable pins min typ max unit test condition reference figure absolute accuracy 3.0 lsbav cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v 6.0 av cc = 2.0 v to 5.5 v v cc = 2.0 v to 5.5 v 8.0 except the above * 4 conversion time 12.4 124 s av cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v 62 124 except the above notes: * 1set av cc = v cc when the a/d converter is not used. * 2ai stop1 is the current in active and sleep modes while the a/d converter is idle. * 3ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. * 4 conversion time 62 s 14.2.5 lcd characteristics table 14.6 shows the lcd characteristics. table 14.6 lcd characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss = av ss = 0.0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications), t a = +75c (die) (including subactive mode) unless otherwise specified. values item symbol a pp licable pins test conditions min typ max unit reference figure segment driver drop voltage v ds seg 1 to seg 32 i d = 2 a v 1 = 2.7 v to 5.5 v 0.6v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 a v 1 = 2.7 v to 5.5 v 0.3v * 1 lcd power supply split-resistance r lcd between v 1 and v ss 0.5 3.0 9.0 m ? liquid crystal display voltage v lcd v 1 2.2 5.5 v * 2 notes: * 1the voltage drop from power supply pins v 1 , v 2 , v 3 , and vss to each segment pin or common pin. * 2 when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v cc v 1 v 2 v 3 v ss .
rev. 4.00, 05/03, page 417 of 562 14.3 h8/38024 f-ztat version and h8/38024r f-ztat version absolute maximum ratings table 14.7 lists the absolute maximum ratings. table 14.7 absolute maximum ratings item symbol value unit note power supply voltage v cc C0.3 to +4.3 v * 1 analog power supply voltage av cc C0.3 to +4.3 v input voltage ports other than port b and irqaec v in C0.3 to v cc +0.3 v port b av in C0.3 to av cc +0.3 v irqaec hv in C0.3 to +7.3 v port 9 pin voltage v p9 C0.3 to +7.3 v operating temperature t opr C20 to +75 * 2 (regular specifications) c C40 to +85 * 2 (wide-range specifications) +75 (products shipped as chips) * 3 c storage temperature t stg C55 to +125 c notes: * 1permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. * 2 the operating temperature ranges for flash memory programming/erasing are t a = C20c to +75c. * 3 power may be applied when the temperature is between C20 and +75 c.
rev. 4.00, 05/03, page 418 of 562 14.4 h8/38024 f-ztat version and h8/38024r f-ztat version electrical characteristics 14.4.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 2.7 3.6 v cc (v) f w (khz) ? all operating 32.768 2.0 10.0 2.7 3.6 v cc (v) fosc (mhz) ? active (high-speed) mode ? sleep (high-speed) mode note 1: the fosc values are those when an oscillator is used; when an external clock is used the minimum value of fosc is 1 mhz.
rev. 4.00, 05/03, page 419 of 562 2. power supply voltage and operating frequency range ? subactive mode ? subsleep mode (except cpu) ? watch mode (except cpu) 16.384 8.192 4.096 2.7 3.6 v cc (v) sub (khz) 19.2 9.6 4.8 (0.5) 5.0 1.0 2.7 3.6 v cc (v) (mhz) (7.8125) 625 15.625 2.7 3.6 v cc (v) (khz) note 1: the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 1 mhz. note 2: the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 15.625 khz. ? active (high-speed) mode ? sleep (high-speed) mode (except cpu) ? active (medium-speed) mode ? sleep (medium-speed) mode (except a/d converter) 3. analog power supply voltage and a/d converter operating range (mhz) (0.5) 5.0 1.0 2.7 3.6 av cc (v) (khz) 500 625 2.7 3.6 av cc (v) ? active (medium-speed) mode ? sleep (medium-speed) mode ? active (high-speed) mode ? sleep (high-speed) mode
rev. 4.00, 05/03, page 420 of 562 14.4.2 dc characteristics table 14.8 lists the dc characteristics of the hd64f38024 and hd64f38024r. table 14.8 dc characteristics v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v values item symbol applicable pins min typ max unit test condition notes input high voltage v ih res , wkp 0 to wkp 7 , irq 0 , irq 1 , irq 3 , irq 4 , aevl, aevh, tmic, tmif, tmig, adtrg , sck 32 0.9 v cc v cc + 0.3 v rxd 32 , ud 0.8 v cc v cc + 0.3 v osc 1 0.9 v cc v cc + 0.3 v x 1 0.9 v cc v cc + 0.3 v p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.8 v cc v cc + 0.3 v pb 0 to pb 7 0.8 v cc av cc + 0.3 v irqaec, p9 5 * 5 0.9 v cc 7.3 v
rev. 4.00, 05/03, page 421 of 562 values item symbol applicable pins min typ max unit test condition notes input low voltage v il res , wkp 0 to wkp 7 , irq 0 , irq 1 , irq 3 , irq 4 , irqaec, p9 5 * 5 , aevl, aevh, tmic, tmif, tmig, adtrg , sck 32 C0.3 0.1 v cc v rxd 32 , ud C0.3 0.2 v cc v osc 1 C0.3 0.1 v cc v x 1 C0.3 0.1 v cc v p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 C0.3 0.2 v cc v v cc C 1.0 v Ci oh = 1.0 ma output high voltage v oh p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc C 0.3 Ci oh = 0.1 ma output low voltage v ol p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.5 vi ol = 0.4 ma p9 0 to p9 2 0.5 vi ol = 25 ma * 1 i ol = 10 ma * 2 p9 3 to p9 5 0.5 vi ol = 10 ma
rev. 4.00, 05/03, page 422 of 562 values item symbol applicable pins min typ max unit test condition notes input/output leakage current | i il | res , p4 3 , osc 1 , x 1 , p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , irqaec, p9 0 to p9 5 , pa 0 to pa 3 1.0 av in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 1.0 av in = 0.5 v to av cc C 0.5 v pull-up mos current Ci p p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p5 0 to p5 7 , p6 0 to p6 7 30 180 a v cc = 3 v, v in = 0 v input capacitance * 6 c in all input pins except power supply and irqaec 15.0 pf f = 1 mhz, v in =0 v, t a = 25c irqaec 30.0 pf active mode current dissipation i ope1 v cc 1.2 ma active (high-speed) mode v cc = 3 v, f osc = 2 mhz * 3 * 4 max. guideline = 1.1 typ. 1.8 ma active (high-speed) mode v cc = 3 v, f osc = 4 mhz * 3 * 4 max. guideline = 1.1 typ. 4.0 6.0 ma active (high-speed) mode v cc = 3 v, f osc = 10 mhz * 3 * 4
rev. 4.00, 05/03, page 423 of 562 values item symbol applicable pins min typ max unit test condition notes active mode current dissipation i ope2 v cc 0.7 ma active (medium- speed) mode v cc = 3 v, f osc = 2 mhz osc /128 * 3 * 4 max. guideline = 1.1 typ. 0.8 ma active (medium- speed) mode v cc = 3 v, f osc = 4 mhz osc /128 * 3 * 4 max. guideline = 1.1 typ. 1.2 1.8 ma active (medium- speed) mode v cc = 3 v, f osc = 10 mhz osc /128 * 3 * 4 i sleep v cc 1.0 mav cc = 3 v, f osc = 2 mhz * 3 * 4 max. guideline = 1.1 typ. sleep mode current dissipation 1.5 mav cc = 3 v, f osc = 4 mhz * 3 * 4 max. guideline = 1.1 typ. 3.24.8 mav cc = 3 v, f osc = 10 mhz * 3 * 4 subactive mode current dissipation i sub v cc 10 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /8) * 3 * 4 reference value 2040 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4
rev. 4.00, 05/03, page 424 of 562 values item symbol applicable pins min typ max unit test condition notes subsleep mode current dissipation i subsp v cc 4.8 16.0 a v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 3 * 4 watch mode current dissipation i watch v cc 2.0 av cc = 2.7 v, t a = 25 c 32 khz crystal oscillator lcd not used * 3 * 4 reference value 2.06.0 av cc = 2.7 v, 32 khz crystal oscillator lcd not used * 3 * 4 standby mode current dissipation i stby v cc 0.3 av cc = 3.0 v, t a = 25 c 32 khz crystal oscillator not used * 3 * 4 reference value 1.0 5.0 a 32 khz crystal oscillator not used * 3 * 4 ram data retaining voltage v ram v cc 2.0 v i ol output pins except port 9 0.5 ma allowable output low current (per pin) p9 0 to p9 2 25.0 ma * 1 10.0 * 2 p9 3 to p9 5 10.0 ma i ol output pins except port 9 20.0 ma allowable output low current (total) port 9 80.0 ma allowable output high current (per pin) Ci oh all output pins 0.2 ma allowable output high current (total) C i oh all output pins 10.0 ma notes: connect the test pin to v ss . * 1applied when the pioff bit in the port mode register 9 is 0. * 2 applied when the pioff bit in the port mode register 9 is 1.
rev. 4.00, 05/03, page 425 of 562 * 3 pin states during current measurement. mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc operates v cc halted active (medium- speed) mode (i ope2 ) sleep mode v cc only on-chip timers operate v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd subactive mode v cc operates v cc halted subsleep mode v cc only on-chip timers operate , cpu stops v cc halted watch mode v cc only time base operates, cpu stops v cc halted system clock oscillator: crystal subclock oscillator: crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd * 4 excludes current in pull-up mos transistors and output buffers. * 5 used for the judgment of user mode or boot mode when the reset is released. *6 except for the package for the tlp-85v (under development).
rev. 4.00, 05/03, page 426 of 562 14.4.3 ac characteristics table 14.9 lists the control signal timing, and tables 14.10 lists the serial interface timing of the h8/38024f. table 14.9 control signal timing v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v values item symbol applicable pins min typ max unit test condition reference figure system clock oscillation frequency f osc osc 1 , osc 2 2.0 10.0 mhz osc clock ( osc ) cycle time t osc osc 1 , osc 2 100 500 (1000) ns figure 14.1 * 2 t cyc 2 128 t osc system clock ( ) cycle time 128 s subclock oscillation frequency f w x 1 , x 2 32.768 or 38.4 khz watch clock ( w ) cycle time t w x 1 , x 2 30.5 or 26.0 s figure 14.1 subclock ( sub ) cycle time t subcyc 2 8 t w * 1 instruction cycle time 2 t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 0.8 2.0 ms figure 14.9 (crystal oscillator) figure 14.9 * 3 2.0 6.0 ms figure 14.8 (crystal oscillator) figure 14.8 * 4 20 45 s figure 14.9 (ceramic oscillator) figure 14.9 * 3 20 45 s figure 14.8 (ceramic oscillator) figure 14.8 * 4 50 ms except the above x 1 , x 2 2.0 s t cph osc 1 40 ns figure 14.1 external clock high width x 1 15.26 or 13.02 s
rev. 4.00, 05/03, page 427 of 562 values item symbol applicable pins min typ max unit test condition reference figure t cpl osc 1 40 ns figure 14.1 external clock low width x 1 15.26 or 13.02 s t cpr osc 1 10 ns figure 14.1 external clock rise time x 1 55.0 ns t cpf osc 1 10 ns figure 14.1 external clock fall time x 1 55.0 ns pin res low width t rel res 10 t cyc figure 14.2 input pin high width t ih irq 0 , irq 1 , irq 3 , irq 4 , irqaec, wkp 0 to wkp 7 , tmic, tmif, tmig, adtrg 2 t cyc t subcyc figure 14.3 aevl, aevh 0.5 t osc input pin low width t il irq 0 , irq 1 , irq 3 , irq 4 , irqaec, wkp 0 to wkp 7 , tmic, tmif, tmig, adtrg 2 t cyc t subcyc figure 14.3 aevl, aevh 0.5 t osc ud pin minimum transition width t udh t udl ud 4 t cyc t subcyc figure 14.6 notes: * 1selected with sa1 and sa0 of system control register 2 (syscr2). * 2 the figure in parentheses applies when an external clock is used. * 3 applies to the hd64f38024r. * 4 applies to the hd64f38024.
rev. 4.00, 05/03, page 428 of 562 table 14.10 serial interface (sci3) timing v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v values item symbol min typ max unit test conditions reference figure asynchronous t scyc 4 t cyc or figure 14.4 input clock cycle synchronous 6 t subcyc input clock pulse width t sckw 0.4 0.6 t scyc figure 14.4 transmit data delay time (synchronous) t txd 1t cyc or t subcyc figure 14.5 receive data setup time (synchronous) t rxs 400.0 ns figure 14.5 receive data hold time (synchronous) t rxh 400.0 ns figure 14.5
rev. 4.00, 05/03, page 429 of 562 14.4.4 a/d converter characteristics table 14.11 shows the a/d converter characteristics of the h8/38024f. table 14.11 a/d converter characteristics v cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v values item symbol applicable pins min typ max unit test condition reference figure analog power supply voltage av cc av cc 2.7 3.6 v * 1 analog input voltage av in an 0 to an 7 C 0.3 av cc + 0.3 v ai ope av cc 1.0 maav cc = 3.0 v analog power supply current ai stop1 av cc 600 a * 2 reference value ai stop2 av cc 5 a * 3 analog input capacitance c ain an 0 to an 7 15.0 pf allowable signal source impedance r ain 10.0 k ? resolution (data length) 10 bit nonlinearity error 3.5 lsbav cc = 2.7 v to 3.6 v quantization error 0.5 lsb absolute accuracy 2.0 4.0 lsb av cc = 2.7 v to 3.6 v conversion time 12.4 124 s av cc = 2.7 v to 3.6 v notes: * 1set av cc = v cc when the a/d converter is not used. * 2ai stop1 is the current in active and sleep modes while the a/d converter is idle. * 3ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle.
rev. 4.00, 05/03, page 430 of 562 14.4.5 lcd characteristics table 14.12 shows the lcd characteristics. table 14.12 lcd characteristics v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v values item symbol a pp licable pins test conditions min typ max unit reference figure segment driver drop voltage v ds seg 1 to seg 32 i d = 2 a v 1 = 2.7 v to 3.6 v 0.6v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 a v 1 = 2.7 v to 3.6 v 0.3v * 1 r lcd 0.5 3.0 9.0 m ? * 3 lcd power supply split-resistance between v 1 and v ss 1.5 3.0 7.0 * 4 liquid crystal display voltage v lcd v 1 2.2 3.6 v * 2 notes: * 1the voltage drop from power supply pins v 1 , v 2 , v 3 , and vss to each segment pin or common pin. * 2 when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v cc v 1 v 2 v 3 v ss . * 3 applies to the hd64f38024. * 4 applies to the hd64f38024r.
rev. 4.00, 05/03, page 431 of 562 14.4.6 flash memory characteristics [preliminary specifications] table 14.13 lists the flash memory characteristics. table 14.13 flash memory characteristics av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, v cc = 2.7 v to 3.6 v (operating voltage range in reading), v cc = 3.0 v to 3.6 v (operating voltage range in programming/erasing), t a = C20 to +75c (operating temperature range in programming/erasing) values item symbol test condition min typ max unit programming time (per 128 bytes) * 1 * 2 * 4 t p 7 200 ms erase time (per block) * 1 * 3 * 6 t e 100 1200 ms maximum number of reprogrammings n wec 1000 * 8 * 11 10000 * 9 times 100 * 8 * 12 10000 * 9 data retention time t drp 10 * 10 years programming wait time after swe bit setting * 1 x 1s wait time after psu bit setting * 1 y 50s wait time after p bit setting * 1 * 4 z11 n 6 28 30 32 s z2 7 n 1000 198 200 202 s z3 additional- programming 8 1012s wait time after p bit clear * 1 5 s wait time after psu bit clear * 1 5 s wait time after pv bit setting * 1 4 s wait time after dummy write * 1 2 s wait time after pv bit clear * 1 2 s wait time after swe bit clear * 1 100 s maximum programming count * 1 * 4 * 5 n 1000times erase wait time after swe bit setting * 1 x 1s wait time after esu bit setting * 1 y 100s wait time after e bit setting * 1 * 6 z 10 100 ms wait time after e bit clear * 1 10s wait time after esu bit clear * 1 10s wait time after ev bit setting * 1 20s wait time after dummy write * 1 2 s wait time after ev bit clear * 1 4 s wait time after swe bit clear * 1 100 s maximum erase count * 1 * 6 * 7 n 120times
rev. 4.00, 05/03, page 432 of 562 notes: * 1make the time settings in accordance with the program/erase algorithms. * 2 the programming time for 128 bytes. (indicates the total time for which the p bit in flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) * 3 the time required to erase one block. (indicates the time for which the e bit in flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) * 4 programming time maximum value (t p (max)) = wait time after p bit setting (z) maximum number of writes (n) * 5 set the maximum number of writes (n) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (t p (max)). the wait time after p bit setting (z1, z2) should be changed as follows according to the value of the number of writes (n). number of writes (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s * 6 erase time maximum value (t e (max)) = wait time after e bit setting (z) maximum number of erases (n) * 7 set the maximum number of erases (n) according to the actual set value of (z), so that it does not exceed the erase time maximum value (t e (max)). * 8 the minimum number of times all characteristics are guaranteed following reprogramming. (the guarantee covers the range from 1 to the minimum value.) * 9 reference value at 25c. (guideline showing number of reprogrammings over which functioning will be retained under normal circumstances.) * 10 data retention characteristics within the range indicated in the specifications, including the minimum value for reprogrammings. * 11 applies to an operating voltage range when reading data of 3.0 to 3.6 v. * 12 applies to an operating voltage range when reading data of 2.7 to 3.6 v.
rev. 4.00, 05/03, page 433 of 562 14.5 h8/38024s group mask rom version absolute maximum ratings table 14.14 lists the absolute maximum ratings. table 14.14 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +4.3 v * 1 analog power supply voltage av cc ?0.3 to +4.3 v input voltage ports other than port b v in ?0.3 to v cc +0.3 v port b av in ?0.3 to av cc +0.3 v port 9 pin voltage v p9 ?0.3 to v cc +0.3 v operating temperature t opr ?20 to +75 (regular specifications) c ?40 to +85 (wide-range specifications) +75 (products shipped as chips) * 2 c storage temperature t stg ?55 to +125 c notes: * 1 permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. * 2 power may be applied when the temperature is between ?20 and +75c.
rev. 4.00, 05/03, page 434 of 562 14.6 h8/38024s group mask rom version electrical characteristics 14.6.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures. 1. power supply voltage and oscillator frequency range 38.4 1.8 2.7 3.6 v cc (v) f w (khz) ? all operating 32.768 2.0 4.0 10.0 2.7 1.8 3.6 v cc (v) fosc (mhz) ? active (high-speed) mode ? sleep (high-speed) mode note 1: the fosc values are those when an oscillator is used; when an external clock is used the minimum value of fosc is 1 mhz.
rev. 4.00, 05/03, page 435 of 562 2. power supply voltage and operating frequency range ? subactive mode ? subsleep mode (except cpu) ? watch mode (except cpu) 16.384 8.192 4.096 1.8 2.7 3.6 v cc (v) sub (khz) 19.2 9.6 4.8 (0.5) 5.0 1.0 2.0 2.7 1.8 3.6 v cc (v) (mhz) note 1: the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 1 mhz. note 2: the figure in parentheses is the minimum operating frequency when an external clock is input. when using an oscillator, the minimum operating frequency ( ) is 15.625 khz. ? active (high-speed) mode ? sleep (high-speed) mode (except cpu) ? active (medium-speed) mode ? sleep (medium-speed) mode (except a/d converter) (7.8125) 625 15.625 250 2.7 1.8 3.6 v cc (v) (mhz) 3. analog power supply voltage and a/d converter operating range (mhz) (0.5) 5.0 1.0 2.7 3.6 av cc (v) 1.8 (khz) 500 625 2.7 1.8 3.6 av cc (v) ? active (medium-speed) mode ? sleep (medium-speed) mode ? active (high-speed) mode ? sleep (high-speed) mode
rev. 4.00, 05/03, page 436 of 562 14.6.2 dc characteristics table 14.15 lists the dc characteristics of the h8/38024s. table 14.15 dc characteristics v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = av ss = 0.0 v values item symbol applicable pins min typ max unit test condition notes input high voltage v ih res , wkp 0 to wkp 7 , irq 0 , irq 1 , irq 3 , irq 4 , aevl, aevh, tmic, tmif, tmig, adtrg , sck 32 0.9 v cc v cc + 0.3 v rxd 32 , ud 0.8 v cc v cc + 0.3 v osc 1 0.9 v cc v cc + 0.3 v x 1 0.9 v cc v cc + 0.3 v p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.8 v cc v cc + 0.3 v pb 0 to pb 7 0.8 v cc av cc + 0.3 v irqaec 0.9 v cc v cc + 0.3 v
rev. 4.00, 05/03, page 437 of 562 values item symbol applicable pins min typ max unit test condition notes input low voltage v il res , wkp 0 to wkp 7 , irq 0 , irq 1 , irq 3 , irq 4 , irqaec, aevl, aevh, tmic, tmif, tmig, adtrg , sck 32 C0.3 0.1 v cc v rxd 32 , ud C0.3 0.2 v cc v osc 1 C0.3 0.1 v cc v x 1 C0.3 0.1 v cc v p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 , pb 0 to pb 7 C0.3 0.2 v cc v output high voltage v oh p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 v cc C 1.0 v cc C 0.3 vCi oh = 1.0 ma v cc = 2.7 v to 3.6 v Ci oh = 0.1 ma output low voltage v ol p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , pa 0 to pa 3 0.5 vi ol = 0.4 ma p9 0 to p9 5 0.5 vi ol = 10 ma v cc = 2.2 v to 3.6 v 0.5 vi ol = 8 ma v cc = 1.8 v to 3.6 v
rev. 4.00, 05/03, page 438 of 562 values item symbol applicable pins min typ max unit test condition notes input/output leakage current | i il | res , p4 3 , osc 1 , x 1 , p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p4 0 to p4 2 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , irqaec, p9 0 to p9 5 , pa 0 to pa 3 1.0 av in = 0.5 v to v cc C 0.5 v pb 0 to pb 7 1.0 av in = 0.5 v to av cc C 0.5 v pull-up mos current Ci p p1 3 , p1 4 , p1 6 , p1 7 , p3 0 to p3 7 , p5 0 to p5 7 , p6 0 to p6 7 30 180 a v cc = 3 v, v in = 0 v input capacitance c in all input pins except power supply and irqaec 15.0 pf f = 1 mhz, v in =0 v, t a = 25c irqaec 30.0 pf i ope1 v cc 0.2 ma active (high-speed) mode v cc = 1.8 v, f osc = 1 mhz * 1 * 2 max. guideline = 1.1 typ. active mode current dissipation 0.6 ma active (high-speed) mode v cc = 3 v, f osc = 2 mhz * 1 * 2 max. guideline = 1.1 typ. 1.2 ma active (high-speed) mode v cc = 3 v, f osc = 4 mhz * 1 * 2 max. guideline = 1.1 typ.
rev. 4.00, 05/03, page 439 of 562 values item symbol applicable pins min typ max unit test condition notes active mode current dissipation i ope1 v cc 3.16.0 ma active (high-speed) mode v cc = 3 v, f osc = 10 mhz * 1 * 2 i ope2 v cc 0.03 ma active (medium- speed) mode v cc = 1.8 v, f osc = 1 mhz osc /128 * 1 * 2 max. guideline = 1.1 typ. 0.1 ma active (medium- speed) mode v cc = 3 v, f osc = 2 mhz osc /128 * 1 * 2 max. guideline = 1.1 typ. 0.2 ma active (medium- speed) mode v cc = 3 v, f osc = 4 mhz osc /128 * 1 * 2 max. guideline = 1.1 typ. 0.6 1.8 ma active (medium- speed) mode v cc = 3 v, f osc = 10 mhz osc /128 * 1 * 2 i sleep v cc 0.08 mav cc = 1.8 v, f osc = 1 mhz * 1 * 2 max. guideline = 1.1 typ. sleep mode current dissipation 0.3 mav cc = 3 v, f osc = 2 mhz * 1 * 2 max. guideline = 1.1 typ.
rev. 4.00, 05/03, page 440 of 562 values item symbol applicable pins min typ max unit test condition notes sleep mode current dissipation i sleep v cc 0.5 mav cc = 3 v, f osc = 4 mhz * 1 * 2 max. guideline = 1.1 typ. 1.34.8 mav cc = 3 v, f osc = 10 mhz * 1 * 2 subactive mode current dissipation i sub v cc 6.2 av cc = 1.8 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 1 * 2 reference value 4.4 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /8) * 1 * 2 reference value 1040 av cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 1 * 2 subsleep mode current dissipation i subsp v cc 4.6 16.0 a v cc = 2.7 v, lcd on 32 khz crystal oscillator ( sub = w /2) * 1 * 2 watch mode current dissipation i watch v cc 1.2 av cc = 1.8 v, t a = 25 c 32 khz crystal oscillator lcd not used * 1 * 2 reference value 2.0 av cc = 2.7 v, t a = 25 c 32 khz crystal oscillator lcd not used * 1 * 2 reference value 2.06.0 av cc = 2.7 v, 32 khz crystal oscillator lcd not used * 1 * 2
rev. 4.00, 05/03, page 441 of 562 values item symbol applicable pins min typ max unit test condition notes standby mode current dissipation i stby v cc 0.1 av cc = 1.8 v, t a = 25 c 32 khz crystal oscillator not used * 1 * 2 reference value 0.3 av cc = 3.0 v, t a = 25 c 32 khz crystal oscillator not used * 1 * 2 reference value 1.0 5.0 a 32 khz crystal oscillator not used * 1 * 2 ram data retaining voltage v ram v cc 1.5 v i ol output pins except port 9 0.5 ma allowable output low current (per pin) p9 0 to p9 5 10.0 ma i ol output pins except port 9 20.0 ma allowable output low current (total) port 9 80.0 ma allowable output high current (per pin) Ci oh all output pins 0.2 ma allowable output high current (total) C i oh all output pins 10.0 ma
rev. 4.00, 05/03, page 442 of 562 notes: connect the test pin to v ss . * 1pin states during current measurement. mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) v cc operates v cc halted system clock oscillator: crystal active (medium- speed) mode (i ope2 ) subclock oscillator: pin x 1 = gnd sleep mode v cc only on-chip timers operate v cc halted subactive mode v cc operates v cc halted system clock oscillator: subsleep mode v cc only on-chip timers operate, cpu stops v cc halted crystal subclock oscillator: watch mode v cc only time base operates, cpu stops v cc halted crystal standby mode v cc cpu and timers both stop v cc halted system clock oscillator: crystal subclock oscillator: pin x 1 = gnd * 2 excludes current in pull-up mos transistors and output buffers. * 3 except for the package for the tlp-85v (under development).
rev. 4.00, 05/03, page 443 of 562 14.6.3 ac characteristics table 14.16 lists the control signal timing, and tables 14.10 lists the serial interface timing of the h8/38024s. table 14.16 control signal timing v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = av ss = 0.0 v values item symbol applicable pins min typ max unit test condition reference figure system clock oscillation frequency f osc osc 1 , osc 2 2.0 ? 10.0 mhz v cc = 2.7 v to 3.6 v 2.0 ? 4.0 mhz v cc = 1.8 v to 3.6 v osc clock ( osc ) cycle time t osc osc 1 , osc 2 100 ? 500 (1000) ns v cc = 2.7 v to 3.6 v figure 14.1 * 2 250 ? 500 (1000) ns v cc = 1.8 v to 3.6 v t cyc 2 ? 128 t osc system clock ( ) cycle time ? ? 128 s subclock oscillation frequency f w x 1 , x 2 ? 32.768 or 38.4 ?khz watch clock ( w ) cycle time t w x 1 , x 2 ? 30.5 or 26.0 ? s figure 14.1 subclock ( sub ) cycle time t subcyc 2? 8 t w * 1 instruction cycle time 2? ? t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 ? 20 45 s ceramic oscillator v cc = 2.2 v to 3.6 v figure 14.9 ? 80 ? s ceramic oscillator except the above ? 0.8 2 ms crystal oscillator v cc = 2.7 v to 3.6 v ? 1.2 3 ms crystal oscillator v cc = 2.2 v to 3.6 v ? ? 50 ms except the above x 1 , x 2 ?? 2 s v cc = 2.2 v to 3.6 v ? 4 ? s except the above
rev. 4.00, 05/03, page 444 of 562 values item symbol applicable pins min typ max unit test condition reference figure t cph osc 1 40 ? ? ns v cc = 2.7 v to 3.6 v figure 14.1 external clock high width 100 ? ? ns v cc = 1.8 v to 3.6 v x 1 ? 15.26 or 13.02 ?s t cpl osc 1 40 ? ? ns v cc = 2.7 v to 3.6 v figure 14.1 external clock low width 100 ? ? ns v cc = 1.8 v to 3.6 v x 1 ? 15.26 or 13.02 ?s t cpr osc 1 ? ? 10 ns v cc = 2.7 v to 3.6 v figure 14.1 external clock rise time ? ? 25 ns v cc = 1.8 v to 3.6 v x 1 ? ? 55.0 ns t cpf osc 1 ? ? 10 ns v cc = 2.7 v to 3.6 v figure 14.1 external clock fall time ? ? 25 ns v cc = 1.8 v to 3.6 v x 1 ? ? 55.0 ns pin res low width t rel res 10 ? ? t cyc figure 14.2 input pin high width t ih irq 0 , irq 1 , irq 3 , irq 4 , irqaec, wkp 0 to wkp 7 , tmic, tmif, tmig, adtrg 2? ? t cyc t subcyc figure 14.3 aevl, aevh 0.5 ? ? t osc input pin low width t il irq 0 , irq 1 , irq 3 , irq 4 , irqaec, wkp 0 to wkp 7 , tmic, tmif, tmig, adtrg 2? ? t cyc t subcyc figure 14.3 aevl, aevh 0.5 ? ? t osc ud pin minimum transition width t udh t udl ud 4 ? ? t cyc t subcyc figure 14.6 notes: * 1 selected with sa1 and sa0 of system control register 2 (syscr2). * 2 the figure in parentheses applies when an external clock is used.
rev. 4.00, 05/03, page 445 of 562 table 14.17 serial interface (sci3) timing v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = av ss = 0.0 v values item symbol min typ max unit test conditions reference figure asynchronous t scyc 4 t cyc or figure 14.4 input clock cycle synchronous 6 t subcyc input clock pulse width t sckw 0.4 0.6 t scyc figure 14.4 transmit data delay time (synchronous) t txd 1t cyc or t subcyc figure 14.5 receive data setup time (synchronous) t rxs 400.0 ns figure 14.5 receive data hold time (synchronous) t rxh 400.0 ns figure 14.5
rev. 4.00, 05/03, page 446 of 562 14.6.4 a/d converter characteristics table 14.18 shows the a/d converter characteristics of the h8/38024s. table 14.18 a/d converter characteristics v cc = 1.8 v to 3.6 v, v ss = av ss = 0.0 v values item symbol applicable pins min typ max unit test condition reference figure analog power supply voltage av cc av cc 1.8 3.6 v * 1 analog input voltage av in an 0 to an 7 C 0.3 av cc + 0.3 v analog power ai ope av cc 1.0 maav cc = 3.0 v supply current ai stop1 av cc 600 a * 2 reference value ai stop2 av cc 5 a * 3 analog input capacitance c ain an 0 to an 7 15.0 pf allowable signal source impedance r ain 10.0 k ? resolution (data length) 10 bit nonlinearity error 3.5 lsbav cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 5.5 lsbav cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v 7.5 lsb other than above * 4 quantization error 0.5 lsb absolute accuracy 4.0 lsbav cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 6.0 lsbav cc = 2.0 v to 3.6 v v cc = 2.0 v to 3.6 v 8.0 lsb other than above * 4 conversion time 12.4 124 s av cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v 62 124 s other than above notes: * 1set av cc = v cc when the a/d converter is not used. * 2ai stop1 is the current in active and sleep modes while the a/d converter is idle. * 3ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. * 4 conversion time: 62 s.
rev. 4.00, 05/03, page 447 of 562 14.6.5 lcd characteristics table 14.19 shows the lcd characteristics. table 14.19 lcd characteristics v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss = av ss = 0.0 v values item symbol a pp licable pins test conditions min typ max unit reference figure segment driver drop voltage v ds seg 1 to seg 32 i d = 2 a v 1 = 2.7 v to 3.6 v 0.6v * 1 common driver drop voltage v dc com 1 to com 4 i d = 2 a v 1 = 2.7 v to 3.6 v 0.3v * 1 lcd power supply split-resistance r lcd between v 1 and v ss 1.5 3.0 7.0 m ? liquid crystal display voltage v lcd v 1 2.2 3.6 v * 2 notes: * 1the voltage drop from power supply pins v 1 , v 2 , v 3 , and vss to each segment pin or common pin. * 2 when the liquid crystal display voltage is supplied from an external power source, ensure that the following relationship is maintained: v cc v 1 v 2 v 3 v ss .
rev. 4.00, 05/03, page 448 of 562 14.7 operation timing figures 14.1 to 14.6 show timing diagrams. t , tw osc v ih v il t cph t cpl t cpr osc1 x 1 t cpf figure 14.1 clock input timing v il t rel figure 14.2 res res res res low width v ih v il t il 0 , 1 , 3 , 4 , tmic, tmif, tmig, , 0 to 7 , irqaec, aevl, aevh t ih figure 14.3 input timing
rev. 4.00, 05/03, page 449 of 562 t scyc t sckw 32 sck figure 14.4 sck3 input clock timing 32 t scyc t txd t rxs t rxh v oh * v ih or v oh * v il or v ol * v ol * oh ol sck txd 32 (transmit data) rxd 32 (receive data) note: * output timing reference levels output high output low load conditions are shown in figure 14.7. v = 1/2vcc + 0.2 v v = 0.8 v figure 14.5 sci3 synchronous mode input/output timing
rev. 4.00, 05/03, page 450 of 562 ud v il v ih t udl t udh figure 14.6 ud pin minimum transition width timing 14.8 output load circuit v cc 2.4 k 12 k 30 pf output pin figure 14.7 output load condition
rev. 4.00, 05/03, page 451 of 562 14.9 resonator equivalent circuit c s c o frequency (mhz) r s (max) c o (max) 4 100 ? 16 pf 4.193 100 ? 16 pf 10 30 ? 16 pf crystal resonator parameters r s osc 2 osc 1 l s frequency (mhz) r s (max) c o (max) 2 18.3 ? 36.94 pf 4 6.8 ? 36.72 pf 10 4.6 ? 32.31 pf ceramic resonator parameters figure 14.8 resonator equivalent circuit (1) osc 1 l s c s c o r s osc 2 crystal resonator parameters (manufacturer's publicly released values) frequency (mhz) r s (max) c o (max) manufacturer nihon dempa kogyo co., ltd. ceramic resonator parameters (1) (manufacturer's publicly released values) frequency (mhz) r s (max) c o (max) manufacturer murata manufacturing co., ltd. manufacturer murata manufacturing co., ltd. 4 100 ? 16 pf 2 18.3 ? 36.94 pf ceramic resonator parameters (2) (manufacturer's publicly released values) frequency (mhz) r s (max) c o (max) 10 4.6 ? 32.31 pf figure 14.9 resonator equivalent circuit (2)
rev. 4.00, 05/03, page 452 of 562 14.10 usage note the ztat, f-ztat, and mask rom versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip rom, layout patterns, and so on. when system evaluation testing is carried out using the ztat or f-ztat version, the same evaluation testing should also be conducted for the mask rom version when changing over to that version.
rev. 4.00, 05/03, page 453 of 562 appendix a cpu instruction set a.1 instructions operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition C subtraction multiplication division logical and logical or exclusive logical or move logical complement condition code notation symbol modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 not affected by the instruction execution result
rev. 4.00, 05/03, page 454 of 562 table a.1 lists the h8/300l cpu instruction set. table a.1 instruction set mnemonic operation i h n z v c mov.b #xx:8, rd b #xx:8 rd8 2 0 2 mov.b rs, rd b rs8 rd8 2 0 2 mov.b @rs, rd b @rs16 rd8 2 0 4 mov.b @(d:16, rs), rd b @(d:16, rs16) rd8 4 0 6 mov.b @rs+, rd b @rs16 rd8 2 0 6 rs16+1 rs16 mov.b @aa:8, rd b @aa:8 rd8 2 0 4 mov.b @aa:16, rd b @aa:16 rd8 4 0 6 mov.b rs, @rd b rs8 @rd16 2 0 4 mov.b rs, @(d:16, rd) b rs8 @(d:16, rd16) 4 0 6 mov.b rs, @ rd b rd16 1 rd16 2 0 6 rs8 @rd16 mov.b rs, @aa:8 b rs8 @aa:8 2 0 4 mov.b rs, @aa:16 b rs8 @aa:16 4 0 6 mov.w #xx:16, rd w #xx:16 rd 4 0 4 mov.w rs, rd w rs16 rd16 2 0 2 mov.w @rs, rd w @rs16 rd16 2 0 4 mov.w @(d:16, rs), rd w @(d:16, rs16) rd16 4 0 6 mov.w @rs+, rd w @rs16 rd16 2 0 6 rs16+2 rs16 mov.w @aa:16, rd w @aa:16 rd16 4 0 6 mov.w rs, @rd w rs16 @rd16 2 0 4 mov.w rs, @(d:16, rd) w rs16 @(d:16, rd16) 4 0 6 mov.w rs, @ rd w rd16 2 rd16 2 0 6 rs16 @rd16 mov.w rs, @aa:16 w rs16 @aa:16 4 0 6 pop rd w @sp rd16 2 0 6 sp+2 sp push rs w sp 2 sp 2 0 6 rs16 @sp #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size
rev. 4.00, 05/03, page 455 of 562 mnemonic operation i h n z v c add.b #xx:8, rd b rd8+#xx:8 rd8 2 2 add.b rs, rd b rd8+rs8 rd8 2 2 add.w rs, rd w rd16+rs16 rd16 2 (1) 2 addx.b #xx:8, rd b rd8+#xx:8 +c rd8 2 (2) 2 addx.b rs, rd b rd8+rs8 +c rd8 2 (2) 2 adds.w #1, rd w rd16+1 rd16 2 2 adds.w #2, rd w rd16+2 rd16 2 2 inc.b rd b rd8+1 rd8 2 2 daa.b rd b rd8 decimal adjust rd8 2 ** (3) 2 sub.b rs, rd b rd8 rs8 rd8 2 2 sub.w rs, rd w rd16 rs16 rd16 2 (1) 2 subx.b #xx:8, rd b rd8 #xx:8 c rd8 2 (2) 2 subx.b rs, rd b rd8 rs8 c rd8 2 (2) 2 subs.w #1, rd w rd16 1 rd16 2 2 subs.w #2, rd w rd16 2 rd16 2 2 dec.b rd b rd8 1 rd8 2 2 das.b rd b rd8 decimal adjust rd8 2 ** 2 neg.b rd b 0 rd rd 2 2 cmp.b #xx:8, rd b rd8 #xx:8 2 2 cmp.b rs, rd b rd8 rs8 2 2 cmp.w rs, rd w rd16 rs16 2 (1) 2 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size
rev. 4.00, 05/03, page 456 of 562 mnemonic operation i h n z v c mulxu.b rs, rd b rd8 rs8 rd16 2 14 divxu.b rs, rd b rd16 rs8 rd16 2 (5) (6) 14 (rdh: remainder, rdl: quotient) and.b #xx:8, rd b rd8 #xx:8 rd8 2 0 2 and.b rs, rd b rd8 rs8 rd8 2 0 2 or.b #xx:8, rd b rd8 #xx:8 rd8 2 0 2 or.b rs, rd b rd8 rs8 rd8 2 0 2 xor.b #xx:8, rd b rd8 #xx:8 rd8 2 0 2 xor.b rs, rd b rd8 rs8 rd8 2 0 2 not.b rd b rd 2 0 2 shal.b rd b 2 2 shar.b rd b 2 02 shll.b rd b 2 02 shlr.b rd b 2 002 rotxl.b rd b 2 02 rotxr.b rd b 2 02 b 7 b 0 0 c c b 7 b 0 b 7 b 0 0 c b 7 b 0 0c c b 7 b 0 c b 7 b 0 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size
rev. 4.00, 05/03, page 457 of 562 mnemonic operation i h n z v c rotl.b rd b 2 02 rotr.b rd b 2 02 bset #xx:3, rd b (#xx:3 of rd8) 12 2 bset #xx:3, @rd b (#xx:3 of @rd16) 14 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) 14 8 bset rn, rd b (rn8 of rd8) 12 2 bset rn, @rd b (rn8 of @rd16) 14 8 bset rn, @aa:8 b (rn8 of @aa:8) 14 8 bclr #xx:3, rd b (#xx:3 of rd8) 02 2 bclr #xx:3, @rd b (#xx:3 of @rd16) 04 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) 04 8 bclr rn, rd b (rn8 of rd8) 02 2 bclr rn, @rd b (rn8 of @rd16) 04 8 bclr rn, @aa:8 b (rn8 of @aa:8) 04 8 bnot #xx:3, rd b (#xx:3 of rd8) 2 2 ( ) bnot #xx:3, @rd b (#xx:3 of @rd16) 4 8 ( ) bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) 4 8 ( ) bnot rn, rd b (rn8 of rd8) 2 2 ( ) bnot rn, @rd b (rn8 of @rd16) 4 8 ( ) bnot rn, @aa:8 b (rn8 of @aa:8) 4 8 ( ) #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size c b 7 b 0 c b 7 b 0
rev. 4.00, 05/03, page 458 of 562 mnemonic operation i h n z v c btst #xx:3, rd b ( ) z2 2 btst #xx:3, @rd b ( ) z4 6 btst #xx:3, @aa:8 b ( ) z4 6 btst rn, rd b ( ) z2 2 btst rn, @rd b ( ) z4 6 btst rn, @aa:8 b ( ) z4 6 bld #xx:3, rd b (#xx:3 of rd8) c2 2 bld #xx:3, @rd b (#xx:3 of @rd16) c4 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) c4 6 bild #xx:3, rd b ( ) c2 2 bild #xx:3, @rd b ( ) c4 6 bild #xx:3, @aa:8 b ( ) c4 6 bst #xx:3, rd b c (#xx:3 of rd8) 2 2 bst #xx:3, @rd b c (#xx:3 of @rd16) 4 8 bst #xx:3, @aa:8 b c (#xx:3 of @aa:8) 4 8 bist #xx:3, rd b (#xx:3 of rd8) 2 2 bist #xx:3, @rd b (#xx:3 of @rd16) 4 8 bist #xx:3, @aa:8 b (#xx:3 of @aa:8) 4 8 band #xx:3, rd b c (#xx:3 of rd8) c2 2 band #xx:3, @rd b c (#xx:3 of @rd16) c4 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 6 biand #xx:3, rd b c ( ) c2 2 biand #xx:3, @rd b c ( ) c4 6 biand #xx:3, @aa:8 b c ( ) c4 6 bor #xx:3, rd b c (#xx:3 of rd8) c2 2 bor #xx:3, @rd b c (#xx:3 of @rd16) c4 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 6 bior #xx:3, rd b c ( ) c2 2 bior #xx:3, @rd b c ( ) c4 6 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size
rev. 4.00, 05/03, page 459 of 562 mnemonic operation i h n z v c bior #xx:3, @aa:8 b c ( ) c4 6 bxor #xx:3, rd b c (#xx:3 of rd8) c2 2 bxor #xx:3, @rd b c (#xx:3 of @rd16) c4 6 bxor #xx:3, @aa:8 b c (#xx:3 of @aa:8) c4 6 bixor #xx:3, rd b c ( ) c2 2 bixor #xx:3, @rd b c ( ) c4 6 bixor #xx:3, @aa:8 b c ( ) c4 6 bra d:8 (bt d:8) pc pc+d:8 2 4 brn d:8 (bf d:8) pc pc+2 2 4 bhi d:8 c z = 0 2 4 bls d:8 c z = 1 2 4 bcc d:8 (bhs d:8) c = 0 2 4 bcs d:8 (blo d:8) c = 1 2 4 bne d:8 z = 0 2 4 beq d:8 z = 1 2 4 bvc d:8 v = 0 2 4 bvs d:8 v = 1 2 4 bpl d:8 n = 0 2 4 bmi d:8 n = 1 2 4 bge d:8 n v = 0 2 4 blt d:8 n v = 1 2 4 bgt d:8 z (n v) = 0 24 ble d:8 z (n v) = 1 24 jmp @rn pc rn16 2 4 jmp @aa:16 pc aa:16 4 6 jmp @@aa:8 pc @aa:8 2 8 bsr d:8 sp 2 sp 2 6 pc @sp pc pc+d:8 #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size if condition is true then pc pc+d:8 else next; branching condition
rev. 4.00, 05/03, page 460 of 562 mnemonic operation i h n z v c jsr @rn sp 2 sp 2 6 pc @sp pc rn16 jsr @aa:16 sp 2 sp 4 8 pc @sp pc aa:16 jsr @@aa:8 sp 2 sp 2 8 pc @sp pc @aa:8 rts pc @sp 2 8 sp+2 sp rte ccr @sp 2 10 sp+2 sp pc @sp sp+2 sp sleep transit to sleep mode. 2 2 ldc #xx:8, ccr b #xx:8 ccr 2 2 ldc rs, ccr b rs8 ccr 2 2 stc ccr, rd b ccr rd8 2 2 andc #xx:8, ccr b ccr #xx:8 ccr 2 2 orc #xx:8, ccr b ccr #xx:8 ccr 2 2 xorc #xx:8, ccr b ccr #xx:8 ccr 2 2 nop pc pc+2 2 2 eepmov if r4l 04 (4) repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l 1 r4l until r4l=0 else next; notes: (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) the number of states required for execution is 4n + 9 (n = value of r4l). 4n + 8 for hd64f38024 and h8/38024s group. (5) set to 1 if the divisor is negative; otherwise cleared to 0. (6) set to 1 if the divisor is zero; otherwise cleared to 0. #xx: 8/16 rn @rn @(d:16, rn) @ rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size
rev. 4.00, 05/03, page 461 of 562 a.2 operation code map table a.2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
rev. 4.00, 05/03, page 462 of 562 table a.2 operation code map high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * note: * the push and pop instructions are identical in machine language to mov instructions. bit-manipulation instructions
rev. 4.00, 05/03, page 463 of 562 a.3 number of execution states the tables here can be used to calculate the number of states required for instruction execution. table a.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table a.3 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 table a.3 number of cycles in each instruction access location execution status (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m internal operation s n 1 note: * depends on which on-chip module is accessed. see section 2.9.1, notes on data access for details.
rev. 4.00, 05/03, page 464 of 562 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1, rd 1 adds.w #2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1
rev. 4.00, 05/03, page 465 of 562 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1
rev. 4.00, 05/03, page 466 of 562 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp. b #xx:8, rd 1 cmp. b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 * inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16, rs), rd 2 1 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 2 1 mov.b rs, @Crd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 2 1 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 note: * n: initial value in r4l. the source and destination operands are accessed n + 1 times each. internal operation n is 0 for hd64f38024.
rev. 4.00, 05/03, page 467 of 562 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 2 1 mov.w rs, @Crd 1 1 2 mov.w rs, @aa:16 2 1 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1, rd 1 subs.w #2, rd 1 pop pop rd 1 1 2 push push rs 1 1 2 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1
rev. 4.00, 05/03, page 468 of 562 appendix b internal i/o registers b.1 addresses upper address: h'f0 bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'20 flmcr1 swe esu psu ev pv e p rom h'21flmcr2fler h'22flpwcrpdwnd h'23 ebr eb4 eb3 eb2 eb1 eb0 h'24 h'25 h'26 h'27 h'28 h'29 h'2a h'2bfenrflshe h'2c h'2d h'2e h'2f
rev. 4.00, 05/03, page 469 of 562 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'80 h'81 h'82 h'83 h'84 h'85 h'86 h'87 h'88 h'89 h'8a h'8b h'8c ecpwcrh ecpwcrh7 ecpwcrh6 ecpwcrh5 ecpwcrh4 ecpwcrh3 ecpwcrh2 ecpwcrh1 ecpwcrh0 asynchronous h'8d ecpwcrl ecpwcrl7 ecpwcrl6 ecpwcrl5 ecpwcrl4 ecpwcrl3 ecpwcrl2 ecpwcrl1 ecpwcrl0 event counter h'8e ecpwdrh ecpwdrh7 ecpwdrh6 ecpwdrh5 ecpwdrh4 ecpwdrh3 ecpwdrh2 ecpwdrh1 ecpwdrh0 h'8f ecpwdrl ecpwdrl7 ecpwdrl6 ecpwdrl5 ecpwdrl4 ecpwdrl3 ecpwdrl2 ecpwdrl1 ecpwdrl0 h'90 wegr wkegs7 wkegs6 wkegs5 wkegs4 wkegs3 wkegs2 wkegs1 wkegs0 system control h'91 spcr spc32 scinv3 scinv2 sci3 h'92 aegsr ahegs1 ahegs0 alegs1 alegs0 aiegs1 aiegs0 ecpwme asynchronous h'93 event counter h'94 eccr ackh1 ackh0 ackl1 ackl0 pwck2 pwck1 pwck0 h'95 eccsr ovh ovl ch2 cueh cuel crch crcl h'96 ech ech7 ech6 ech5 ech4 ech3 ech2 ech1 ech0 h'97 ecl ecl7 ecl6 ecl5 ecl4 ecl3 ecl2 ecl1 ecl0 h'98 h'99 h'9a h'9b h'9c h'9d h'9e h'9f
rev. 4.00, 05/03, page 470 of 562 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'a0 h'a1 h'a2 h'a3 h'a4 h'a5 h'a6 h'a7 h'a8 smr com chr pe pm stop mp cks1 cks0 sci3 h'a9 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 h'aa scr3 tie rie te re mpie teie cke1 cke0 h'ab tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 h'ac ssr tdre rdrf oer fer per tend mpbr mpbt h''ad rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 h'ae h'af h'b0tmatma3tma2tma1tma0timer a h'b1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 h'b2 tcsrw b6wi tcwe b4wi tcsrwe b2wi wdon bowi wrst watchdog h'b3 tcw tcw7 tcw6 tcw5 tcw4 tcw3 tcw2 tcw1 tcw0 timer h'b4 tmc tmc7 tmc6 tmc5 _ _ tmc2 tmc1 tmc0 timer c h'b5 tcc/tlc tcc7/tlc7 tcc6/tlc6 tcc5/tlc5 tcc4/tlc4 tcc3/tlc3 tcc2/tlc2 tcc1/tlc1 tcc0/tlc0 h'b6 tcrf tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 timer f h'b7 tcsrf ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl h'b8 tcfh tcfh7 tcfh6 tcfh5 tcfh4 tcfh3 tcfh2 tcfh1 tcfh0 h'b9 tcfl tcfl7 tcfl6 tcfl5 tcfl4 tcfl3 tcfl2 tcfl1 tcfl0 h'ba ocrfh ocrfh7 ocrfh6 ocrfh5 ocrfh4 ocrfh3 ocrfh2 ocrfh1 ocrfh0 h'bb ocrfl ocrfl7 ocrfl6 ocrfl5 ocrfl4 ocrfl3 ocrfl2 ocrfl1 ocrfl0 h'bc tmg ovfh ovfl ovie iiegs cclr1 cclr0 cks1 cks0 timer g h'bd icrgf icrgf7 icrgf6 icrgf5 icrgf4 icrgf3 icrgf2 icrgf1 icrgf0 h'be icrgr icrgr7 icrgr6 icrgr5 icrgr4 icrgr3 icrgr2 icrgr1 icrgr0 h'bf
rev. 4.00, 05/03, page 471 of 562 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'c0 lpcr dts1 dts0 cmx sgs3 sgs2 sgs1 sgs0 lcd controller/ h'c1 lcr psw act disp cks3 cks2 cks1 cks0 driver h'c2lcr2lcdab h'c3 h'c4 adrrh adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 a/d converter h'c5 adrrl adr1 adr0 h'c6 amr cks trge ch3 ch2 ch1 ch0 h'c7adsradsf h'c8 pmr1 irq3 irq4 tmig i/o port h'c9 pmr2 pof1 wdcks ncs irq0 h'ca pmr3 aevl aevh tmofhtmoflud h'cb h'cc pmr5 wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 h'cdpwcr2pwcr21pwcr2010 bit pwm2 h'ce pwdru2 pw dru21 pwdru20 h'cf pwdrl2 pwdrl27 pwdrl26 pwdrl25 pwdrl24 pwdrl23 pwdrl22 pwdrl21 pwdrl20 h'd0pwcr1pwcr11pwcr1010 bit pwm1 h'd1 pwdru1 pw dru11 pwdru10 h'd2 pwdrl1 pwdrl17 pwdrl16 pwdrl15 pwdrl14 pwdrl13 pwdrl12 pwdrl11 pwdrl10 h'd3 h'd4 pdr1 p17 p16 p14 p13 i/o port h'd5 h'd6 pdr3 p37 p36 p35 p34 p33 p32 p31 p30 h'd7pdr4p43p42p41p40 h'd8 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 h'd9 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 h'da pdr7 p77 p76 p75 p74 p73 p72 p71 p70 h'db pdr8 p87 p86 p85 p84 p83 p82 p81 p80 h'dc pdr9 p95 p94 p93 p92 p91 p90 h'ddpdrapa3pa2pa1pa0 h'de pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'df
rev. 4.00, 05/03, page 472 of 562 upper address: h'ff bit names lower address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name h'e0 pucr1 pucr17 pucr16 pucr14 pucr13 i/o port h'e1 pucr3 pucr37 pucr36 pucr35 pucr34 pucr33 pucr32 pucr31 pucr30 h'e2 pucr5 pucr57 pucr56 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 h'e3 pucr6 pucr67 pucr66 pucr65 pucr64 pucr63 pucr62 pucr61 pucr60 h'e4 pcr1 pcr17 pcr16 pcr14 pcr13 h'e5 h'e6 pcr3 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 h'e7pcr4pcr42pcr41pcr40 h'e8 pcr5 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 h'e9 pcr6 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 h'ea pcr7 pcr77 pcr76 pcr75 pcr74 pcr73 pcr72 pcr71 pcr70 h'eb pcr8 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 h'ecpmr9pioffpwm2pwm1 h'edpcrapcra3pcra2pcra1pcra0 h'eepmrbirq1 h'ef h'f0 syscr1 ssby sts2 sts1 sts0 lson ma1 ma0 system control h'f1syscr2n esel dton mson sa1 sa0 h'f2iegrieg4ieg3ieg1ieg0 h'f3 ienr1 ienta ienwpien4 ien3 ienec2 ien1 ien0 h'f4 ienr2 iendt ienad ientg ientfh ientfl ientc ienec h'f5 h'f6 irr1 irrta irri4 irri3 irrec2 irri1 irri0 h'f7 irr2 irrdt irrad irrtg irrtfh irrtfl irrtc irrec h'f8 h'f9 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 system control h'fa ckstpr1 s32ckstp adckstp tgckstp tfckstp tcckstp tackstp h'fbckstpr2pw2ckstp aeckstp wdckstp pw1ckstp ldckstp h'fc h'fd h'fe h'ff legend sci: serial communication interface
rev. 4.00, 05/03, page 473 of 562 b.2 functions bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 0 w tcrf timer control register f hb6 timer f toggle output level l set to low level set to high level 16-bit mode, counts on tcfl overflow signal internal clock: /32 internal clock: /16 internal clock: /4 internal clock: w /4 0 1 toggle output level h 0 1 set to low level set to high level clock select h 0 1 1 1 1 * 0 0 1 1 * 0 1 0 1 counts on external event (tmif) rising/ falling edge clock select l 1 1 1 1 0 0 1 1 0 1 0 1 internal clock: /32 internal clock: /16 internal clock: /4 internal clock: w /4 0 ** * dont care r w r/w read only write only read and write see relevant register description possible types of access initial bit values dashes ( ) indicate undefined bits. bit numbers register acronym register name address to which the register is mapped. when displayed with two-digit number, this indicates the lower address, and the upper address is hff. name of on-chip supporting module names of the bits. dashes ( ) indicate reserved bits. full name of bit descriptions of bit settings
rev. 4.00, 05/03, page 474 of 562 flmcr1flash memory control register 1 h'f020 flash memory bit initial value read/write 7 0 6 swe 0 r/w 5 esu 0 r/w 0 p 0 r/w 2 pv 0 r/w 1 e 0 r/w 4 psu 0 r/w program 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when swe = 1 and psu = 1 erase 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when swe = 1 and esu = 1 program-verify 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when swe = 1 erase-verify 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when swe = 1 program-setup 0 program-setup cleared (initial value) 1 program setup [setting condition] when swe = 1 erase-setup 0 erase-setup cleared (initial value) 1 erase setup [setting condition] when swe = 1 software write enable bit 0 writing/erasing disabled (initial value) 1 writing/erasing enabled 3 ev 0 r/w
rev. 4.00, 05/03, page 475 of 562 flmcr2flash memory control register 2 h'f021 flash memory bit initial value read/write note: a write to flmcr2 is prohibited. 7 fler 0 r 6 0 5 0 0 0 2 0 1 0 4 0 flash memory error 3 0 flpwcrflash memory power control register h'f022 flash memory bit initial value read/write 7 pdwnd 0 r/w 6 0 5 0 0 0 2 0 1 0 4 0 power-down disable 0 when the system transits to sub-active mode, the flash memory changes to low-power mode 1 when the system transits to sub-active mode, the flash memory changes to normal mode 3 0
rev. 4.00, 05/03, page 476 of 562 ebrerase block register h'f023 flash memory bit initial value read/write note: set the bit of ebr to h00 when erasing. 7 0 6 0 5 0 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w 4 eb4 0 r/w blocks 4 to 0 0 when a block of eb4 to eb0 is not selected (initial value) 1 when a block of eb4 to eb0 is selected 3 eb3 0 r/w fenrflash memory enable register h'f02b flash memory bit initial value read/write 7 flshe 0 r/w 6 0 5 0 0 0 2 0 1 0 4 0 flash memory control register enable 0 the flash memory control register cannot be accessed 1 the flash memory control register can be accessed 3 0
rev. 4.00, 05/03, page 477 of 562 ecpwcrhevent counter pwm compare register h h'8c aec bit initial value r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 ecpwcrh7 ecpwcrh6 ecpwcrh5 ecpwcrh4 ecpwcrh3 ecpwcrh2 ecpwcrh1 ecpwcrh0 1 r/w sets event counter pwm waveform conversion period ecpwcrlevent counter pwm compare register l h'8d aec ecpwcrl7 ecpwcrl6 ecpwcrl5 ecpwcrl4 ecpwcrl3 ecpwcrl2 ecpwcrl1 ecpwcrl0 11111111 bit initial value r/w 7 r/w 6 r/w 5 r/w 4 r/w 3 r/w 2 r/w 1 r/w 0 r/w sets event counter pwm waveform conversion period ecpwdrhevent counter pwm data register h h'8e aec ecpwdrh7 ecpwdrh6 ecpwdrh5 ecpwdrh4 ecpwdrh3 ecpwdrh2 ecpwdrh1 ecpwdrh0 bit initial value r/w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w controls event counter pwm waveform generator data ecpwdrlevent counter pwm data register l h'8f aec bit initial value r/w 76543210 ecpwdrl7 ecpwdrl6 ecpwdrl5 ecpwdrl4 ecpwdrl3 ecpwdrl2 ecpwdrl1 ecpwdrl0 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 w controls event counter pwm waveform generator data
rev. 4.00, 05/03, page 478 of 562 wegrwakeup edge select register h'90 system control bit initial value read/write 7 wkegs7 0 r/w 6 wkegs6 0 r/w 5 wkegs5 0 r/w 0 wkegs0 0 r/w 2 wkegs2 0 r/w 1 wkegs1 0 r/w 4 wkegs4 0 r/w wkpn edge selected 0 pin falling edge detected (n = 7 to 0) 1 pin rising edge detected 3 wkegs3 0 r/w
rev. 4.00, 05/03, page 479 of 562 spcrserial port control register h'91 sci3 bit initial value read/write 7 1 6 1 5 spc32 0 r/w 0 w 2 scinv2 0 r/w 1 w 4 w rxd 32 pin input data inversion switch 0 rxd 32 input data is not inverted 1 rxd 32 input data is inverted txd 32 pin output data inversion switch 0 txd 32 output data is not inverted 1 txd 32 output data is inverted p4 2 /txd 32 pin function switch 0 function as p4 2 i/o pin 1 function as txd 32 output pin 3 scinv3 0 r/w
rev. 4.00, 05/03, page 480 of 562 aegsrinput pin edge selection register h'92 aec bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 ahegs1 ahegs0 alegs1 alegs0 aiegs1 aiegs0 ecpwme 0 r/w event counter pwm enable/disable, irqaec select/deselect 0 1 aec pwm halted, irqaec selected aec pwm operation enabled, irqaec deselected irqaec edge select bit 2 aiegs0 0 1 0 1 bit 3 aiegs1 0 0 1 1 falling edge on irqaec pin is sensed rising edge on irqaec pin is sensed both edges on irqaec pin are sensed use prohibited description aec edge select l bit 4 alegs0 0 1 0 1 bit 5 alegs1 0 0 1 1 falling edge on aevl pin is sensed rising edge on aevl pin is sensed both edges on aevl pin are sensed use prohibited description aec edge select h bit 6 ahegs0 0 1 0 1 bit 7 ahegs1 0 0 1 1 falling edge on aevh pin is sensed rising edge on aevh pin is sensed both edges on aevh pin are sensed use prohibited description
rev. 4.00, 05/03, page 481 of 562 eccrevent counter control register h'94 aec bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w r/w 1 0 0 ackh1 ackh0 ackl1 ackl0 pwck2 pwck1 pwck0 0 r/w event counter pwm clock select bit 2 pwck1 0 0 1 1 * * bit 3 pwck2 0 0 0 0 1 1 /2 /4 /8 /16 /32 /64 description * : dont care bit 1 pwck0 0 1 0 1 0 1 aec clock select l bit 4 ackl0 0 1 0 1 bit 5 ackl1 0 0 1 1 aevl pin input /2 /4 /8 description aec clock select h bit 6 ackh0 0 1 0 1 bit 7 ackh1 0 0 1 1 aevh pin input /2 /4 /8 description
rev. 4.00, 05/03, page 482 of 562 eccsrevent counter control/status register h'95 aec bit initial value read/write 7 ovh 0 r/w 6 ovl 0 r/w 5 0 r/w 0 crcl 0 r/w 2 cuel 0 r/w 1 crch 0 r/w 4 ch2 0 r/w counter reset control l 0 1 ecl is reset ecl reset is cleared and count-up function is enabled counter reset control h 0 ech is reset 1 ech reset is cleared and count-up function is enabled count-up enable l 0 ecl event clock input is disabled. ecl value is held 1 ecl event clock input is enabled count-up enable h 0 ech event clock input is disabled. ech value is held 1 ech event clock input is enabled channel select 0 ech and ecl are used together as a single- channel 16-bit event counter 1 ech and ecl are used as two independent 8-bit event counter channels counter overflow l 0 ecl has not overflowed 1 ecl has overflowed counter overflow h 0 ech has not overflowed 1 ech has overflowed 3 cueh 0 r/w
rev. 4.00, 05/03, page 483 of 562 echevent counter h h'96 aec bit initial value read/write 7 ech7 0 r 6 ech6 0 r 5 ech5 0 r 0 ech0 0 r 2 ech2 0 r 1 ech1 0 r 4 ech4 0 r count value 3 ech3 0 r note: ech and ecl can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (ec). eclevent counter l h'97 aec bit initial value read/write 7 ecl7 0 r 6 ecl6 0 r 5 ecl5 0 r 0 ecl0 0 r 2 ecl2 0 r 1 ecl1 0 r 4 ecl4 0 r 3 ecl3 0 r count value note: ech and ecl can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (ec).
rev. 4.00, 05/03, page 484 of 562 smrserial mode register h'a8 sci3 bit initial value read/write 7 com 0 r/w 6 chr 0 r/w 5 pe 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 4 pm 0 r/w clock select 0 0 01 1 1 1 clock w /2 clock 0 /16 clock /64 clock multiprocessor mode 0 multiprocessor communication function disabled 1 multiprocessor communication function enabled stop bit length 0 1 stop bit 1 2 stop bits parity mode 0 even parity 1 odd parity parity enable 0 parity bit addition and checking disabled 1 parity bit addition and checking enabled character length 0 8-bit data/5-bit data 1 7-bit data/5-bit data communication mode 0 asynchronous mode 1 synchronous mode 3 stop 0 r/w
rev. 4.00, 05/03, page 485 of 562 brrbit rate register h'a9 sci3 bit initial value read/write 7 brr7 1 r/w 6 brr6 1 r/w 5 brr5 1 r/w 4 brr4 1 r/w 3 brr3 1 r/w 0 brr0 1 r/w 2 brr2 1 r/w 1 brr1 1 r/w serial transmit/receive bit rate
rev. 4.00, 05/03, page 486 of 562 scr3serial control register3 h'aa sci3 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 4 re 0 r/w receive interrupt enable 0 receive data full interrupt request (rxi) and receive error interrupt request (eri) disabled 1 receive data full interrupt request (rxi) and receive error interrupt request (eri) enabled multiprocessor interrupt enable 0 multiprocessor interrupt request disabled (normal receive operation) [clearing condition] when data is received in which the multiprocessor bit is set to 1 1 multiprocessor interrupt request enabled the receive interrupt request (rxi), receive error interrupt request (eri), and setting of the rdrf, fer, and oer flags in the serial status register (ssr), are disabled until data with the multiprocessor bit set to 1 is received. transmit enable 0 transmit operation disabled (txd 32 pin is i/o port) 1 transmit operation enabled (txd 32 pin is transmit data pin) receive enable 0 receive operation disabled (rxd 32 pin is i/o port) 1 receive operation enabled (rxd 32 pin is receive data pin) transmit end interrupt enable clock enable 0 bit 1 cke1 0 0 1 1 bit 0 cke0 0 1 0 1 communication mode asynchronous synchronous asynchronous synchronous asynchronous synchronous asynchronous synchronous internal clock internal clock internal clock reserved (do not specify this combination) external clock external clock reserved (do not specify this combination) reserved (do not specify this combination) i/o port serial clock output clock output clock input serial clock input clock source sck 32 pin function description transmit end interrupt request (tei) disabled 1 transmit end interrupt request (tei) enabled transmit interrupt enable 0 transmit data empty interrupt request (txi) disabled 1 transmit data empty interrupt request (txi) enabled 3 mpie 0 r/w
rev. 4.00, 05/03, page 487 of 562 tdrtransmit data register h'ab sci3 bit initial value read/write 7 tdr7 1 r/w 6 tdr6 1 r/w 5 tdr5 1 r/w 4 tdr4 1 r/w 3 tdr3 1 r/w 0 tdr0 1 r/w 2 tdr2 1 r/w 1 tdr1 1 r/w data for transfer to tsr
rev. 4.00, 05/03, page 488 of 562 ssrserial status register h'ac sci3 bit initial value read/write note: * only a write of 0 for flag clearing is possible. 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 oer 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpbr 0 r 4 fer 0 r/(w) * receive data register full 0 there is no receive data in rdr [clearing conditions] ? after reading rdrf = 1, cleared by writing 0 to rdrf ? when rdr data is read by an instruction 1 there is receive data in rdr [setting condition] when reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 transmit data written in tdr has not been transferred to tsr [clearing conditions] ? after reading tdre = 1, cleared by writing 0 to tdre ? when data is written to tdr by an instruction 1 transmit data has not been written to tdr, or transmit data written in tdr has been transferred to tsr [setting conditions] ? when bit te in serial control register3 (scr3) is cleared to 0 ? when data is transferred from tdr to tsr transmit end 0 transmission in progress [clearing conditions] 1 transmission ended [setting conditions] parity error 0 reception in progress or completed normally [clearing condition] after reading per = 1, cleared by writing 0 to per 1 a parity error has occurred during reception [setting condition] framing error 0 reception in progress or completed normally [clearing condition] after reading fer = 1, cleared by writing 0 to fer 1 a framing error has occurred during reception [setting condition] when the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 overrun error 0 reception in progress or completed [clearing condition] after reading oer = 1, cleared by writing 0 to oer 1 an overrun error has occurred during reception [setting condition] when the next serial reception is completed with rdrf set to 1 multiprocessor bit receive multiprocessor bit transfer 0 data in which the multiprocessor bit is 0 has been received 1 data in which the multiprocessor bit is 1 has been received 0 a 0 multiprocessor bit is transmitted 1 a 1 multiprocessor bit is transmitted 3 per 0 r/(w) * ? after reading tdre = 1, cleared by writing 0 to tdre ? when data is written to tdr by an instruction ? when bit te in serial control register3 (scr3) is cleared to 0 ? when bit tdre is set to 1 when the last bit of a transmit character is sent when the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (pm) in the serial mode register (smr)
rev. 4.00, 05/03, page 489 of 562 rdrreceive data register h'ad sci3 bit initial value read/write 7 rdr7 0 r 6 rdr6 0 r 5 rdr5 0 r 4 rdr4 0 r 3 rdr3 0 r 0 rdr0 0 r 2 rdr2 0 r 1 rdr1 0 r serial receiving data are stored tmatimer mode register a h'b0 timer a bit initial value read/write 7 w 6 w 5 w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w internal clock select tma3 tma2 0 pss pss pss pss 0 4 1 tma1 0 1 tma0 0 0 1 1 pss pss pss pss 10 1 0 0 1 1 1 psw psw psw psw 00 1 0 0 1 1 psw and tca are reset 10 1 0 0 1 1 prescaler and divider ratio or overflow period /8192 /4096 /2048 /512 /256 /128 /32 /8 1 s 0.5 s 0.25 s 0.03125 s interval timer clock time base (when using 32.768 khz) function 3 tma3 0 r/w
rev. 4.00, 05/03, page 490 of 562 tcatimer counter a h'b1 timer a bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value
rev. 4.00, 05/03, page 491 of 562 tcsrwtimer control/status register w h'b2 watchdog timer bit initial value read/write 7 b6wi 1 r 6 tcwe 0 r/(w) * 5 b4wi 1 r 3 b2wi 1 r 0 wrst 0 r/(w) * 2 wdon 0 r/(w) * 1 bowi 1 r 4 tcsrwe 0 r/(w) * watchdog timer reset 0 clearing conditions: reset by pin when tcsrwe = 1, and 0 is written in both b0wi and wrst 1 setting condition: when tcw overflows and an internal reset signal is generated watchdog timer on 0 watchdog timer operation is disabled clearing conditions: reset, or 0 is written in both b2wi and wdon while tcsrwe = 1 1 watchdog timer operation is enabled setting condition: 0 is written in b2wi and 1 is written in wdon while tcsrwe = 1 bit 0 write inhibit 0 bit 0 is write-enabled 1 bit 0 is write-disabled bit 2 write inhibit 0 bit 2 is write-enabled 1 bit 2 is write-disabled timer control/status register w write enable 0 data cannot be written to bits 2 and 0 1 data can be written to bits 2 and 0 bit 4 write inhibit 0 bit 4 is write-enabled 1 bit 4 is write-disabled timer counter w write enable 0 8-bit data cannot be written to tcw 1 8-bit data can be written to tcw bit 6 write inhibit 0 bit 6 is write-enabled 1 bit 6 is write-disabled note: * write is permitted only under certain conditions.
rev. 4.00, 05/03, page 492 of 562 tcwtimer counter w h'b3 watchdog timer bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w 4 tcw4 0 r/w count value tmctimer mode register c h'b4 timer c bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 1 clock select 000 1 10 1 100 1 10 1 internal clock: /8192 internal clock: /2048 internal clock: /512 internal clock: /64 internal clock: /16 internal clock: /4 internal clock: w /4 external event (tmic): rising or falling edge counter up/down control 0 tcc is an up-counter 0 0 1 tcc is a down-counter 1 * hardware control of tcc up/down operation by ud pin input ud pin input high: down-counter ud pin input low: up-counter auto-reload function select 0 interval timer function selected 1 auto-reload function selected * : dont care
rev. 4.00, 05/03, page 493 of 562 tcctimer counter c h'b5 timer c bit initial value read/write note: tcc is allocated to the same address as tlc. in a read, the tcc value is returned. 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r 4 tcc4 0 r count value tlctimer load register c h'b5 timer c bit initial value read/write note: tlc is allocated to the same address as tcc. in a write, the value is written to tlc. 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w 4 tlc4 0 w reload value
rev. 4.00, 05/03, page 494 of 562 tcrftimer control register f h'b6 timer f bit initial value read/write 7 tolh 0 w 6 cksh2 0 w 5 cksh1 0 w 0 cksl0 0 w 2 cksl2 0 w 1 cksl1 0 w 4 cksh0 0 w clock select l do not specify this combination internal clock /32 internal clock /16 internal clock /4 internal clock w /4 counting on external event (tmif) rising/falling edge toggle output level l 0 low level 1 high level toggle output level h 0 low level 1 high level 3 toll 0 w clock select h 0 except for 11 do not specify this combination internal clock /32 internal clock /16 internal clock /4 internal clock w /4 16-bit mode, counting on tcfl overflow signal 1 1 1 1 0 0 1 1 0 011 1 0 1 0 0 1 1 1 1 except for 11 1 0 0 1 1 1 0 1 0 1
rev. 4.00, 05/03, page 495 of 562 tcsrftimer control/status register f h'b7 timer f bit initial value read/write note: * bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. 7 ovfh 0 r/(w) * 6 cmfh 0 r/(w) * 5 ovieh 0 r/w 0 cclrl 0 r/w 2 cmfl 0 r/(w) * 1 oviel 0 r/w 4 cclrh 0 r/w compare match flag h 0 clearing condition: after reading cmfh = 1, cleared by writing 0 to cmfh 1 setting condition: set when the tcfh value matches the ocrfh value timer overflow flag h 0 clearing condition: after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting condition: set when tcfh overflows from hff to h00 compare match flag l 0 clearing condition: after reading cmfl = 1, cleared by writing 0 to cmfl 1 setting condition: set when the tcfl value matches the ocrfl value timer overflow flag l 0 clearing condition: after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting condition: set when tcfl overflows from hff to h00 counter clear h 0 16-bit mode: tcf clearing by compare match is disabled 8-bit mode: tcfh clearing by compare match is disabled 1 16-bit mode: tcf clearing by compare match is enabled 8-bit mode: tcfh clearing by compare match is enabled timer overflow interrupt enable h 0 tcfh overflow interrupt request is disabled 1 tcfh overflow interrupt request is enabled timer overflow interrupt enable l counter clear l 0 tcfl overflow interrupt request is disabled 1 tcfl overflow interrupt request is enabled 0 tcfl clearing by compare match is disabled 1 tcfl clearing by compare match is enabled 3 ovfl 0 r/(w) *
rev. 4.00, 05/03, page 496 of 562 tcfh8-bit timer counter fh h'b8 timer f bit initial value read/write 7 tcfh7 0 r/w 6 tcfh6 0 r/w 5 tcfh5 0 r/w 4 tcfh4 0 r/w 3 tcfh3 0 r/w 0 tcfh0 0 r/w 2 tcfh2 0 r/w 1 tcfh1 0 r/w count value note: tcfh and tcfl can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (tcf). tcfl8-bit timer counter fl h'b9 timer f bit initial value read/write 7 tcfl7 0 r/w 6 tcfl6 0 r/w 5 tcfl5 0 r/w 4 tcfl4 0 r/w 3 tcfl3 0 r/w 0 tcfl0 0 r/w 2 tcfl2 0 r/w 1 tcfl1 0 r/w count value note: tcfh and tcfl can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (tcf). ocrfhoutput compare register fh h'ba timer f bit initial value read/write 7 ocrfh7 1 r/w 6 ocrfh6 1 r/w 5 ocrfh5 1 r/w 4 ocrfh4 1 r/w 3 ocrfh3 1 r/w 0 ocrfh0 1 r/w 2 ocrfh2 1 r/w 1 ocrfh1 1 r/w note: ocrfh and ocrfl can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (ocrf).
rev. 4.00, 05/03, page 497 of 562 ocrfloutput compare register fl h'bb timer f bit initial value read/write 7 ocrfl7 1 r/w 6 ocrfl6 1 r/w 5 ocrfl5 1 r/w 4 ocrfl4 1 r/w 3 ocrfl3 1 r/w 0 ocrfl0 1 r/w 2 ocrfl2 1 r/w 1 ocrfl1 1 r/w note: ocrfh and ocrfl can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (ocrf).
rev. 4.00, 05/03, page 498 of 562 tmgtimer mode register g h'bc timer g bit initial value read/write 7 ovfh 0 r/(w) * 6 ovfl 0 r/(w) * 5 ovie 0 r/w 3 cclr1 0 r/w 0 cks0 0 r/w 2 cclr0 0 r/w 1 cks1 0 r/w 4 iiegs 0 r/w timer overflow flag l 0 clearing condition: after reading ovfl = 1, cleared by writing 0 to ovfl 1 setting condition: set when tcg overflows from hff to h00 timer overflow flag h 0 clearing condition: after reading ovfh = 1, cleared by writing 0 to ovfh 1 setting condition: set when tcg overflows from hff to h00 input capture interrupt edge select 0 interrupt generated on rising edge of input capture input signal 1 interrupt generated on falling edge of input capture input signal timer overflow interrupt enable 0 tcg overflow interrupt request is disabled 1 tcg overflow interrupt request is enabled clock select 0 internal clock: counting on /64 0 1 internal clock: counting on /32 1 0 internal clock: counting on /2 1 internal clock: counting on w /4 counter clear 0 tcg clearing is disabled 0 1 tcg cleared by falling edge of input capture input signal 1 0 tcg cleared by rising edge of input capture input signal 1 tcg cleared by both edges of input capture input signal note: * bits 7 and 6 can only be written with 0, for flag clearing.
rev. 4.00, 05/03, page 499 of 562 icrgfinput capture register gf h'bd timer g bit initial value read/write 7 icrgf7 0 r 6 icrgf6 0 r 5 icrgf5 0 r 3 icrgf3 0 r 0 icrgf0 0 r 2 icrgf2 0 r 1 icrgf1 0 r 4 icrgf4 0 r stores tcg value at falling edge of input capture signal icrgrinput capture register gr h'be timer g bit initial value read/write 7 icrgr7 0 r 6 icrgr6 0 r 5 icrgr5 0 r 3 icrgr3 0 r 0 icrgr0 0 r 2 icrgr2 0 r 1 icrgr1 0 r 4 icrgr4 0 r stores tcg value at rising edge of input capture signal
rev. 4.00, 05/03, page 500 of 562 lpcrlcd port control register h'c0 lcd controller/driver duty select, common function select bit 7 dts1 0 0 1 1 bit 6 dts0 0 1 0 1 bit 5 cmx 0 1 0 1 0 1 0 1 duty cycle static 1/2 duty 1/3 duty 1/4 duty common drivers com 1 com 4 to com 1 com 2 to com 1 com 4 to com 1 com 3 to com 1 com 4 to com 1 com 4 to com 1 do not use com 4 to com 2 com 4 to com 2 output the same waveform as com 1 do not use com 4 and com 3 com 4 outputs the same waveform as com 3 and com 2 outputs the same waveform as com 1 do not use com 4 do not use com 4 notes bit initial value read/write 7 dts1 0 r/w 6 dts0 0 r/w 5 cmx 0 r/w 0 sgs0 0 r/w 2 sgs2 0 r/w 1 sgs1 0 r/w 4 w segment driver select 3 sgs3 0 r/w port port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port port seg seg seg seg seg seg seg seg port port port port port port bit 3 0 1 sgs3 bit 2 0 1 0 1 sgs2 bit 1 0 1 0 1 0 1 0 1 sgs1 bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sgs0 seg 32 to seg 29 seg 28 to seg 25 seg 24 to seg 21 seg 20 to seg 17 seg 16 to seg 13 seg 12 to seg 9 seg 8 to seg 5 port seg seg seg seg seg seg seg seg port port port port port port port seg 4 to seg 1 function of pins seg 32 to seg 1 note (initial value)
rev. 4.00, 05/03, page 501 of 562 lcrlcd control register h'c1 lcd controller/driver bit initial value read/write 7 1 6 psw 0 r/w 5 act 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 4 disp 0 r/w lcd drive power supply on/off control frame frequency select operating clock bit 1 bit 2 bit 3 0 0 0 1 1 1 1 1 1 1 1 * * * 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 * 0 1 0 1 0 1 0 1 bit 1 cks1 cks2 cks3 cks0 w w /2 w /4 /2 /4 /8 /16 /32 /64 /128 /256 display function activate lcd controller/driver operation halted lcd controller/driver operates * : dont care 0 1 0 lcd drive power supply off 1 lcd drive power supply on display data control 0 blank data is displayed 1 lcd ram data is displayed
rev. 4.00, 05/03, page 502 of 562 lcr2lcd control register 2 h'c2 lcd bit initial value read/write 7 lcdab 0 r/w 6 1 5 1 3 w 0 w 2 w 1 w 4 w a waveform/b waveform switching control 0 drive using a waveform 1 drive using b waveform
rev. 4.00, 05/03, page 503 of 562 amra/d mode register h'c6 a/d converter bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select no channel selected bit 3 0 bit 2 analog input channel * : dont care ch3 ch2 0 ch1 ch0 bit 1 bit 0 0an 1 1 0 1 1 00 external trigger select 0 disables start of a/d conversion by external trigger 1 enables start of a/d conversion by rising or falling edge of external trigger at pin 5 1 4 an 5 an 6 an ** 11 qhhhh 7 ** 100 1 10 1 an 0 an 1 an 2 an 3 clock select 62/ bit 7 0 conversion period cks 31/ 1 62 s = 1 mhz 31 s 12.4 s = 5 mhz conversion time note: * operation is not guaranteed with a conversion time of less than 12.4 s. select a setting that gives a conversion time of at least 12.4 s.
rev. 4.00, 05/03, page 504 of 562 adrrha/d result register h h'c4 a/d converter adrrla/d result register l h'c5 bit initial value read/write adrrh 7 adr9 undefined r 6 adr8 undefined r 5 adr7 undefined r 3 adr5 undefined r 0 adr2 undefined r 2 adr4 undefined r 1 adr3 undefined r 4 adr6 undefined r a/d conversion result bit initial value read/write adrrl 7 adr1 undefined r 6 adr0 undefined r a/d conversion result adsra/d start register h'c7 a/d converter bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 a/d start flag 0 1 read write read write indicates completion of a/d conversion stops a/d conversion indicates a/d conversion in progress starts a/d conversion
rev. 4.00, 05/03, page 505 of 562 pmr1port mode register 1 h'c8 i/o port bit initial value read/write 7 irq3 0 r/w 6 1 5 w 3 tmig 0 r/w 0 w 2 w 1 1 4 irq4 0 r/w p1 3 /tmig pin function switch 0 functions as p1 3 i/o pin 1 functions as tmig input pin p1 4 /irq 4 /adtrg pin function switch 0 functions as p1 4 i/o pin 1 functions as 4 / input pin p1 7 /irq 3 /tmif pin function switch 0 functions as p1 7 i/o pin 1 functions as 3 /tmif input pin
rev. 4.00, 05/03, page 506 of 562 pmr2port mode register 2 h'c9 i/o port bit initial value read/write 7 1 6 1 5 pof1 0 r/w 4 1 3 1 0 irq0 0 r/w 2 wdcks 0 r/w 1 ncs 0 r/w p4 3 /irq0 pin function switch 0 functions as p4 3 i/o pin 1 functions as 0 input pin tmig noise canceller select 0 noise cancellation function not used 1 noise cancellation function used watchdog timer switch 0 selects 8192 1 selects w /32 p3 5 pin output buffer pmos on/off control 0 cmos output 1 nmos open-drain output
rev. 4.00, 05/03, page 507 of 562 pmr3port mode register 3 h'ca i/o port bit initial value read/write 7 aevl 0 r/w 6 aevh 0 r/w 5 w 3 w 0 ud 0 r/w 2 tmofh 0 r/w 1 tmofl 0 r/w 4 w p3 2 /tmofh pin function switch 0 functions as p3 2 i/o pin 1 functions as tmofh output pin p3 1 /tmofl pin function switch 0 functions as p3 1 i/o pin 1 functions as tmofl output pin p3 0 /ud pin function switch 0 functions as p3 0 i/o pin 1 functions as ud input pin p3 6 /aevh pin function switch 0 functions as p3 6 i/o pin functions as aevh input pin 1 p3 7 /aevl pin function switch 0 functions as p3 7 i/o pin 1 functions as aevl input pin
rev. 4.00, 05/03, page 508 of 562 pmr5port mode register 5 h'cc i/o port bit initial value read/write 7 wkp 7 0 r/w 6 wkp 6 0 r/w 5 wkp 5 0 r/w 3 wkp 3 0 r/w 0 wkp 0 0 r/w 2 wkp 2 0 r/w 1 wkp 1 0 r/w 4 wkp 4 0 r/w 0 functions as p5 n i/o pin (n = 7 to 0) p5 n /wkp n /seg n+1 pin function switch 1 functions as n input pin pwcr2pwm2 control register h'cd 10-bit pwm clock select 0 1 0 1 the input clock is (t * = 1/ ) the conversion period is 512/ , with a minimum modulation width of 1/2 the input clock is /2 (t * = 2/ ) the conversion period is 1,024/ , with a minimum modulation width of 1/ the input clock is /4 (t * = 4/ ) the conversion period is 2,048/ , with a minimum modulation width of 2/ the input clock is /8 (t * = 8/ ) the conversion period is 4,096/ , with a minimum modulation width of 4/ note: * t : period of pwm2 input clock 0 1 bit initial value read/write 7 1 6 1 5 1 3 1 0 pwcr20 0 w 2 1 1 pwcr21 0 w 4 1 pwdru2pwm2 data register u h'ce 10-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 2 1 1 0 w 0 pwdru21 pwdru20 0 w upper 2 bits of pwm2 waveform generation data
rev. 4.00, 05/03, page 509 of 562 pwdrl2pwm2 data register l h'cf 10-bit pwm lower 8 bits of pwm2 waveform generation data bit initial value read/write 7 pwdrl27 0 w 6 pwdrl26 0 w 5 pwdrl25 0 w 3 pwdrl23 0 w 0 pwdrl20 0 w 2 pwdrl22 0 w 1 pwdrl21 0 w 4 pwdrl24 0 w pwcr1pwm1 control register h'd0 10-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr10 0 w 2 1 1 pwcr11 0 w clock select 0 the input clock is (t * = 1/ ) the conversion period is 512/ , with a minimum modulation width of 1/2 the input clock is /2 (t * = 2/ ) the conversion period is 1,024/ , with a minimum modulation width of 1/ 1 the input clock is /4 (t * = 4/ ) the conversion period is 2,048/ , with a minimum modulation width of 2/ the input clock is /8 (t * = 8/ ) the conversion period is 4,096/ , with a minimum modulation width of 4/ note: * t : period of pwm input clock
rev. 4.00, 05/03, page 510 of 562 pwdru1pwm1 data register u h'd1 10-bit pwm bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 0 w 2 1 1 0 w upper 2 bits of data for generating pwm1 waveform pwdru10 pwdru11 pwdrl1pwm1 data register l h'd2 10-bit pwm bit initial value read/write 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w lower 8 bits of data for generating pwm1 waveform pwdrl15 pwdrl14 pwdrl13 pwdrl10 pwdrl12 pwdrl11 pwdrl16 pwdrl17 pdr1port data register 1 h'd4 i/o ports bit initial value read/write 7 p1 7 0 r/w data for port 1 pins 6 p1 6 0 r/w 5 3 p1 3 0 r/w 0 2 1 4 p1 4 0 r/w pdr3port data register 3 h'd6 i/o ports bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 0 r/w 2 p3 0 r/w 1 p3 0 r/w 2 3 4 5 6 7 1 data for port 3 pins
rev. 4.00, 05/03, page 511 of 562 pdr4port data register 4 h'd7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 p4 1 r 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 30 21 data for port 4 pins reads p4 3 state pdr5port data register 5 h'd8 i/o ports bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 30 21 4 5 6 7 data for port 5 pins pdr6port data register 6 h'd9 i/o ports bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 30 21 4 5 6 7 data for port 6 pins pdr7port data register 7 h'da i/o ports bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 3210 4 5 6 7 data for port 7 pins
rev. 4.00, 05/03, page 512 of 562 pdr8port data register 8 h'db i/o ports bit initial value read/write 7 p8 7 0 r/w 6 p8 6 0 r/w 5 p8 5 0 r/w 4 p8 4 0 r/w 3 p8 3 0 r/w 0 p8 0 0 r/w 2 p8 2 0 r/w 1 p8 1 0 r/w data for port 8 pins pdr9port data register 9 h'dc i/o ports bit initial value read/write 7 1 6 1 5 p9 5 1 r/w 4 p9 4 1 r/w 3 p9 3 1 r/w 0 p9 0 1 r/w 2 p9 2 1 r/w 1 p9 1 1 r/w data for port 9 pins pdraport data register a h'dd i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pa 0 r/w 0 pa 0 r/w 2 pa 0 r/w 1 pa 0 r/w 30 21 data for port a pins pdrbport data register b h'de i/o ports bit read/write 7 pb 7 r 6 pb 6 r 5 pb 5 r 4 pb 4 r 3 pb 3 r 0 pb 0 r 2 pb 2 r 1 pb 1 r read port b pin states
rev. 4.00, 05/03, page 513 of 562 pucr1port pull-up control register 1 h'e0 i/o ports bit initial value read/write 7 pucr1 7 0 r/w 6 pucr1 6 0 r/w 0 1 input pull-up mos is off input pull-up mos is on 5 w 3 pucr1 3 0 r/w 0 w 2 w 1 w 4 pucr1 4 0 r/w port 1 input pull-up mos control note: when the pcr1 specification is 0. (input port specification) pucr3port pull-up control register 3 h'e1 i/o ports bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 2 3 4 5 6 7 10 0 1 input pull-up mos is off input pull-up mos is on port 3 input pull-up mos control note: when the pcr3 specification is 0. (input port specification)
rev. 4.00, 05/03, page 514 of 562 pucr5port pull-up control register 5 h'e2 i/o ports bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 30 21 4 5 6 7 0 1 input pull-up mos is off input pull-up mos is on port 5 input pull-up mos control note: when the pcr5 specification is 0. (input port specification) pucr6port pull-up control register 6 h'e3 i/o ports bit initial value read/write 7 pucr6 0 r/w 6 pucr6 0 r/w 5 pucr6 0 r/w 4 pucr6 0 r/w 3 pucr6 0 r/w 0 pucr6 0 r/w 2 pucr6 0 r/w 1 pucr6 0 r/w 30 21 4 5 6 7 0 1 input pull-up mos is off input pull-up mos is on port 6 input pull-up mos control note: when the pcr6 specification is 0. (input port specification) pcr1port control register 1 h'e4 i/o ports bit initial value read/write 7 pcr1 7 0 w 6 pcr1 6 0 w 5 w 3 pcr1 3 0 w 0 w 2 w 1 w 4 pcr1 4 0 w port 1 input/output select 0 input pin 1 output pin
rev. 4.00, 05/03, page 515 of 562 pcr3port control register 3 h'e6 i/o ports bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w port 3 input/output select 0 input pin 1 output pin 2 3 4 5 6 7 10 pcr4port control register 4 h'e7 i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w port 4 input/output select 0 input pin 1 output pin 0 21 pcr5port control register 5 h'e8 i/o ports bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w port 5 input/output select 0 input pin 1 output pin 76543 0 21
rev. 4.00, 05/03, page 516 of 562 pcr6port control register 6 h'e9 i/o ports bit initial value read/write 7 pcr6 0 w 6 pcr6 0 w 5 pcr6 0 w 4 pcr6 0 w 3 pcr6 0 w 0 pcr6 0 w 2 pcr6 0 w 1 pcr6 0 w port 6 input/output select 0 input pin 1 output pin 76543 0 21 pcr7port control register 7 h'ea i/o ports bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w port 7 input/output select 0 input pin 1 output pin 7 65 432 10 pcr8port control register 8 h'eb i/o ports bit initial value read/write 7 pcr8 7 0 w 6 pcr8 6 0 w 5 pcr8 5 0 w 4 pcr8 4 0 w 3 pcr8 3 0 w 0 pcr8 0 w 2 pcr8 2 0 w 1 pcr8 1 0 w port 8 input/output select 0 input pin 1 output pin 0
rev. 4.00, 05/03, page 517 of 562 pmr9port mode register 9 h'ec i/o ports p90/pwm1 pin function switch functions as p90 output pin functions as pwm1 output pin 0 1 p91/pwm2 pin function switch functions as p91 output pin functions as pwm2 output pin 0 1 p92 to p90 step-up circuit control large-current port step-up circuit is turned on large-current port step-up circuit is turned off 0 1 bit initial value read/write note: * readable/writable reserved bit in the h8/38024s group. 7 1 6 1 5 1 4 1 3 pioff/ * 0 r/w 0 pwm1 0 r/w 2 w 1 pwm2 0 r/w
rev. 4.00, 05/03, page 518 of 562 pcraport control register a h'ed i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 pcra 0 w 0 pcra 0 w 2 pcra 0 w 1 pcra 0 w 0 1 2 3 port a input/output select 0 input pin 1 output pin pmrbport mode register b h'ee i/o ports bit initial value read/write 7 1 6 1 5 1 4 1 3 irq1 0 r/w 0 1 2 1 1 1 0 functions as pb 3 /an 3 input pin 1 functions as 1 input pin pb 3 /an 3 /irq 1 pin function switch
rev. 4.00, 05/03, page 519 of 562 syscr1system control register 1 h'f0 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 3 lson 0 r/w 0 ma0 1 r/w 2 1 1 ma1 1 r/w 4 sts0 0 r/w software standby 0 ? when a sleep instruction is executed in active mode, a transition is made to sleep mode 1 standby timer select 2 to 0 0 wait time = 8,192 states wait time = 16,384 states 0 0 1 wait time = 1,024 states wait time = 2,048 states 10 1 active (medium-speed) mode clock select osc /16 osc /32 0 1 0 0 1 1 osc /64 osc /128 1 1 00 10 1 wait time = 4,096 states wait time = 2 states wait time = 8 states wait time = 16 states low speed on flag 0 the cpu operates on the system clock ( ) 1 the cpu operates on the subclock ( ) sub ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode ? when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode
rev. 4.00, 05/03, page 520 of 562 syscr2system control register 2 h'f1 system control bit initial value read/write 7 1 6 1 5 1 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 4 nesel 1 r/w subactive mode clock select 0 w /8 w /4 0 1 1 w /2 * direct transfer on flag 0 ? when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode 1 ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode ? when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 medium speed on flag 0 operates in active (high-speed) mode 1 operates in active (medium-speed) mode noise elimination sampling frequency select 0 sampling rate is osc /16 1 sampling rate is osc /4 * : dont care
rev. 4.00, 05/03, page 521 of 562 iegrirq edge select register h'f2 system control bit initial value read/write 7 1 6 1 4 ieg4 0 r/w 3 ieg3 0 r/w 0 ieg0 0 r/w 2 w 1 ieg1 0 r/w 5 1 irq 0 edge select 0 falling edge of 0 pin input is detected rising edge of 0 pin input is detected 1 irq 1 edge select 0 falling edge of 1 , tmic pin input is detected rising edge of 1 , tmic pin input is detected 1 irq 3 edge select 0 falling edge of 3 , tmif pin input is detected rising edge of 3 , tmif pin input is detected 1 irq 4 edge select 0 falling edge of 4 , pin input is detected rising edge of 4 , pin input is detected 1
rev. 4.00, 05/03, page 522 of 562 ienr1interrupt enable register 1 h'f3 system control bit initial value read/write 7 ienta 0 r/w 6 w 4 ien4 0 r/w 3 ien3 0 r/w 0 ien0 0 r/w 2 ienec2 0 r/w 1 ien1 0 r/w 5 ienwp 0 r/w irqaec interrupt enable 0 disables irqaec interrupt requests enables irqaec interrupt requests 1 irq 4 and irq 3 interrupt enable 0 disables 4 and 3 interrupt requests enables 4 and 3 interrupt requests 1 timer a interrupt enable 0 disables timer a interrupt requests enables timer a interrupt requests 1 wakeup interrupt enable 0 disables 7 to 0 interrupt requests enables 7 to 0 interrupt requests 1 irq 1 to irq 0 interrupt enable 0 disables 1 to 0 interrupt, requests enables 1 to 0 interrupt requests 1
rev. 4.00, 05/03, page 523 of 562 ienr2interrupt enable register 2 h'f4 system control bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 w 3 ientfh 0 r/w 0 ienec 0 r/w 2 ientfl 0 r/w 1 ientc 0 r/w 4 ientg 0 r/w asynchronous event counter interrupt enable 0 disables asynchronous event counter interrupt requests 1 enables asynchronous event counter interrupt requests timer fl interrupt enable 0 disables timer fl interrupt requests 1 enables timer fl interrupt requests timer fh interrupt enable 0 disables timer fh interrupt requests 1 enables timer fh interrupt requests timer c interrupt enable 0 disables timer c interrupt requests 1 enables timer c interrupt requests timer g interrupt enable 0 disables timer g interrupt requests 1 enables timer g interrupt requests a/d converter interrupt enable 0 disables a/d converter interrupt requests 1 enables a/d converter interrupt requests direct transition interrupt enable 0 disables direct transition interrupt requests 1 enables direct transition interrupt requests
rev. 4.00, 05/03, page 524 of 562 irr1interrupt request register 1 h'f6 system control bit initial value read/write 7 irrta 0 r/(w) * 6 w 5 1 3 irri3 0 r/(w) * 0 irri0 0 r/(w) * 2 irrec2 0 r/(w) * 1 irri1 0 r/(w) * 4 irri4 0 r/(w) * irq1 and irq0 interrupt request flags 0 clearing condition: when irrin = 1, it is cleared by writing 0 (n = 1 or 0) note: * bits 7 and 4 to 0 can only be written with 0, for flag clearing. 1 setting condition: when pin is designated for interrupt input and the designated signal edge is input irq4 and irq3 interrupt request flags 0 clearing condition: when irrim = 1, it is cleared by writting 0 (m = 4 or 3) 1 setting condition: when pin is designated for interrupt input and the designated signal edge is input timer a interrupt request flag 0 clearing condition: when irrta = 1, it is cleared by writing 0 1 setting condition: when the timer a counter value overflows (from hff to h00) irqaec interrupt request flag 0 clearing condition: when irrec2 = 1, it is cleared by writing 0 1 setting condition: when pin irqaec is designated for interrupt input and the designated signal edge is input
rev. 4.00, 05/03, page 525 of 562 irr2interrupt request register 2 h'f7 system control bit initial value read/write 7 irrdt 0 r/(w) * 6 irrad 0 r/(w) * 5 w 3 irrtfh 0 r/(w) * 0 irrec 0 r/(w) * 2 irrtfl 0 r/(w) * 1 irrtc 0 r/(w) * 4 irrtg 0 r/(w) * note: * bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing. a/d converter interrupt request flag 0 clearing condition: when irrad = 1, it is cleared by writing 0 1 setting condition: when the a/d converter completes conversion and adsf is reset direct transition interrupt request flag 0 clearing condition: when irrdt = 1, it is cleared by writing 0 1 setting condition: when a sleep instruction is executed while dton is set to 1, and a direct transition is made timer fh interrupt request flag 0 clearing condition: when irrtfh = 1, it is cleared by writing 0 1 setting conditions: when counter fh and output compare register fh match in 8-bit timer mode, or when 16-bit counters fl and fh and output compare registers fl and fh match in 16-bit timer mode timer fl interrupt request flag 0 clearing condition: when irrtfl = 1, it is cleared by writing 0 1 setting condition: when counter fl and output compare register fl match in 8-bit timer mode timer g interrupt request flag 0 clearing condition: when irrtg = 1, it is cleared by writing 0 1 setting conditions: when the tmig pin is designated for tmig input and the designated signal edge is input, and when tcg overflows while ovie is set to 1 in tmg timer c interrupt request flag 0 clearing condition: when irrtc = 1, it is cleared by writing 0 1 setting condition: when the timer c counter value overflows (from hff to h00) or underflows (from h00 to hff) asynchronous event counter interrupt request flag 0 clearing condition: when irrec = 1, it is cleared by writing 0 1 setting condition: when the asynchronous event counter value overflows
rev. 4.00, 05/03, page 526 of 562 iwprwakeup interrupt request register h'f9 system control bit initial value read/write 7 iwpf7 0 r/(w) * 6 iwpf6 0 r/(w) * 5 iwpf5 0 r/(w) * 3 iwpf3 0 r/(w) * 0 iwpf0 0 r/(w) * 2 iwpf2 0 r/(w) * 1 iwpf1 0 r/(w) * 4 iwpf4 0 r/(w) * 0 clearing condition: when iwpfn = 1, it is cleared by writing 0 (n = 7 to 0) note: * all bits can only be written with 0, for flag clearing. wakeup interrupt request register 1 setting condition: when pin is designated for wakeup input and a falling edge is input at that pin
rev. 4.00, 05/03, page 527 of 562 ckstpr1clock stop register 1 h'fa system control bit initial value read/write 7 1 6 1 5 s32ckstp 1 r/w 3 tgckstp 1 r/w 0 tackstp 1 r/w 2 tfckstp 1 r/w 1 tcckstp 1 r/w 4 adckstp 1 r/w timer a module standby mode control timer f module standby mode control 0 timer f is set to module standby mode timer f module standby mode is cleared 1 a/d converter module standby mode control 0 a/d converter is set to module standby mode a/d converter module standby mode is cleared 1 0 timer a is set to module standby mode timer a module standby mode is cleared 1 timer c module standby mode control 0 timer c is set to module standby mode timer c module standby mode is cleared 1 timer g module standby mode control 0 timer g is set to module standby mode timer g module standby mode is cleared 1 sci3 module standby mode control 0 sci3 is set to module standby mode sci3 module standby mode is cleared 1
rev. 4.00, 05/03, page 528 of 562 ckstpr2clock stop register 2 h'fb system control bit initial value read/write 7 1 6 1 5 1 3 aeckstp 1 r/w 0 ldckstp 1 r/w 2 wdckstp 1 r/w 1 pw1ckstp 1 r/w 4 pw2ckstp 1 r/w lcd module standby mode control pwm2 module standby mode control 0 pwm2 is set to module standby mode pwm2 module standby mode is cleared 1 asynchronous event counter module standby mode control 0 asynchronous event counter is set to module standby mode asynchronous event counter module standby mode is cleared 1 pwm1 module standby mode control 0 pwm1 is set to module standby mode pwm1 module standby mode is cleared 1 wdt module standby mode control 0 wdt is set to module standby mode wdt module standby mode is cleared 1 0 lcd is set to module standby mode lcd module standby mode is cleared 1
rev. 4.00, 05/03, page 529 of 562 appendix c i/o port block diagrams c.1 block diagrams of port 1 p1 n v cc v cc pucr1 n pmr1 n pdr1 n pcr1 n internal data bus (low level during reset and in standby mode) v ss m pdr1: pcr1: pmr1: pucr1: n = 7 and 4 m = 4 and 3 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 figure c.1(a) port 1 block diagram (pins p1 7 and p1 4 )
rev. 4.00, 05/03, page 530 of 562 v cc v cc (low level during reset and in standby mode) v ss pucr1 6 pmr1 6 pdr1 6 pcr1 6 internal data bus p1 6 pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 figure c.1(b) port 1 block diagram (pin p1 6 )
rev. 4.00, 05/03, page 531 of 562 v cc v cc v ss pucr1 3 pmr1 3 pdr1 3 pcr1 3 timer g module tmig internal data bus p1 3 pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 figure c.1(c) port 1 block diagram (pin p1 3 )
rev. 4.00, 05/03, page 532 of 562 c.2block diagrams of port 3 p3 n v cc v cc pucr3 n pmr3 n pdr3 n pcr3 n aec module internal data bus v ss aevh(p3 6 ) aevl(p3 7 ) pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 n = 7 and 6 figure c.2(a) port 3 block diagram (pins p3 7 and p3 6 )
rev. 4.00, 05/03, page 533 of 562 p3 5 v cc v cc pucr3 5 pmr2 5 pdr3 5 pcr3 5 v ss internal data bus pdr3: pcr3: pucr3: pmr2 port data register 3 port control register 3 port pull-up control register 3 port mode register 2 figure c.2(b) port 3 block diagram (pin p3 5 )
rev. 4.00, 05/03, page 534 of 562 p3 n pdr3 n pucr3 n pcr3 n v ss pdr3: port data register 3 pcr3: port control register 3 n = 4 and 3 internal data bus v cc v cc figure c.2(c) port 3 block diagram (pins p3 4 and p3 3 )
rev. 4.00, 05/03, page 535 of 562 p3 n v cc v cc pucr3 n internal data bus pmr3 n pdr3 n pcr3 n v ss pdr3: port data register 3 pcr3: port control register 3 pmr3: port mode register 3 pucr3: port pull-up control register 3 n = 2 and 1 tmofh (p3 2 ) tmofl (p3 1 ) figure c.2(d) port 3 block diagram (pins p3 2 and p3 1 )
rev. 4.00, 05/03, page 536 of 562 v cc v cc v ss pucr3 0 pdr3 0 pcr3 0 ud internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 p3 0 timer c module pmr3 0 figure c.2(e) port 3 block diagram (pin p3 0 )
rev. 4.00, 05/03, page 537 of 562 c.3 block diagrams of port 4 p4 3 pmr2 0 internal data bus 0 pmr2: port mode register 2 figure c.3(a) port 4 block diagram (pin p4 3 )
rev. 4.00, 05/03, page 538 of 562 p4 2 sci3 module internal data bus pdr4 2 scinv3 pcr4 2 v ss pdr4: port data register 4 pcr4: port control register 4 txd32 v cc spc32 figure c.3(b) port 4 block diagram (pin p4 2 )
rev. 4.00, 05/03, page 539 of 562 p4 1 v cc sci3 module pdr4 1 pcr4 1 v ss pdr4: port data register 4 pcr4: port control register 4 re32 rxd32 internal data bus scinv2 figure c.3(c) port 4 block diagram (pin p4 1 )
rev. 4.00, 05/03, page 540 of 562 p4 0 v cc sci3 module pdr4 0 pcr4 0 v ss pdr4: port data register 4 pcr4: port control register 4 sckie32 sckoe32 scko32 internal data bus scki32 figure c.3(d) port 4 block diagram (pin p4 0 )
rev. 4.00, 05/03, page 541 of 562 c.4 block diagram of port 5 p5 n v cc v cc pucr5 n internal data bus pmr5 n pdr5 n pcr5 n * v ss n pdr5: port data register 5 pcr5: port control register 5 pmr5: port mode register 5 pucr5: port pull-up control register 5 n = 7 to 0 note: * the value of is fixed at 1 in the hd64f38024. figure c.4 port 5 block diagram
rev. 4.00, 05/03, page 542 of 562 c.5 block diagram of port 6 p6 n v cc v cc pucr6 n pdr6 n internal data bus pcr6 n v ss pdr6: port data register 6 pcr6: port control register 6 pucr6: port pull-up control register 6 n = 7 to 0 figure c.5 port 6 block diagram
rev. 4.00, 05/03, page 543 of 562 c.6 block diagram of port 7 p7 n v cc pdr7 n internal data bus pcr7 n v ss pdr7: port data register 7 pcr7: port control register 7 n = 7 to 0 figure c.6 port 7 block diagram
rev. 4.00, 05/03, page 544 of 562 c.7 block diagram of port 8 p8 n v cc pdr8 n internal data bus pcr8 n v ss pdr8: pcr8: n = 7 to 0 port data register 8 port control register 8 figure c.7 port 8 block diagram
rev. 4.00, 05/03, page 545 of 562 c.8 block diagrams of port 9 p9 n pdr9 n pmr9 n v ss pdr9: n = 1 and 0 port data register 9 pwm module pwm n+1 internal data bus figure c.8(a) port 9 block diagram (pins p9 1 and p9 0 ) p9 n pdr9 n v ss pdr9: n = 5 to 2 port data register 9 internal data bus figure c.8(b) port 9 block diagram (pins p9 5 to p9 2 )
rev. 4.00, 05/03, page 546 of 562 c.9 block diagram of port a pa n v cc pdra n internal data bus pcra n v ss pdra: port data register a pcra: port control register a n = 3 to 0 figure c.9 port a block diagram
rev. 4.00, 05/03, page 547 of 562 c.10 block diagram of port b pb n internal data bus amr3 to amr0 a/d module v in n = 7 to 0 dec figure c.10 port b block diagram
rev. 4.00, 05/03, page 548 of 562 appendix d port states in the different processing states table d.1 port states overview port reset sleep subsleep standby watch subactive active p1 7 , p1 6 , p1 4 , p1 3 high impedance retained retained high impedance * 1 retained functions functions p3 7 to p3 0 high impedance retained retained high impedance * 1 retained functions functions p4 3 to p4 0 high impedance retained retained high impedance retained functions functions p5 7 to p5 0 high impedance retained retained high impedance * 1 * 2 retained functions functions p6 7 to p6 0 high impedance retained retained high impedance * 1 retained functions functions p7 7 to p7 0 high impedance retained retained high impedance retained functions functions p8 7 to p8 0 high impedance retained retained high impedance retained functions functions p9 5 to p9 0 high impedance retained retained high impedance * 1 retained functions functions pa 3 to pa 0 high impedance retained retained high impedance retained functions functions pb 7 to pb 0 high impedance high impedance high impedance high impedance high impedance high impedance high impedance notes: * 1 high level output when mos pull-up is in on state. * 2 in the hd64f38024 the previous pin state is retained.
rev. 4.00, 05/03, page 549 of 562 appendix e list of product codes table e.1 h8/38024 group product code lineup product type product code mark code package (package code) h8/38024 hd64338024h hd64338024( *** )h 80-pin qfp (fp-80a) h8/38024 group mask rom versions regular specifications hd64338024f hd64338024( *** )f 80-pin qfp (fp-80b) hd64338024w hd64338024( *** )w 80-pin tqfp (tfp-80c) hcd64338024 die hd64338024d hd64338024( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338024e hd64338024( *** )f 80-pin qfp (fp-80b) hd64338024wi hd64338024( *** )w 80-pin tqfp (tfp-80c) hd64738024h hd64738024h 80-pin qfp (fp-80a) ztat versions regular specifications hd64738024f hd64738024f 80-pin qfp (fp-80b) hd64738024w hd64738024w 80-pin tqfp (tfp-80c) hd64738024d hd64738024h 80-pin qfp (fp-80a) wide-range specifications hd64738024e hd64738024f 80-pin qfp (fp-80b) hd64738024wi hd64738024w 80-pin tqfp (tfp-80c) hd64f38024h hd64f38024h 80-pin qfp (fp-80a) f-ztat versions regular specifications hd64f38024rh hd64f38024h hd64f38024f hd64f38024f 80-pin qfp (fp-80b) hd64f38024rf hd64f38024f hd64f38024w hd64f38024w 80-pin tqfp (tfp-80c) hd64f38024rw hd64f38024w hd64f38024rlpv f38024rlpv 85-pin tflga (tlp-85v) hcd64f38024 die hcd64f38024r hd64f38024d hd64f38024h 80-pin qfp (fp-80a) wide-range specifications hd64f38024rd hd64f38024h hd64f38024e hd64f38024f 80-pin qfp (fp-80b) hd64f38024re hd64f38024f hd64f38024wi hd64f38024w 80-pin tqfp (tfp-80c) hd64f38024rwi hd64f38024w hd64f38024rlpiv f38024rlpiv 85-pin tflga (tlp-85v) h8/38023 hd64338023h hd64338023( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338023f hd64338023( *** )f 80-pin qfp (fp-80b) hd64338023w hd64338023( *** )w 80-pin tqfp (tfp-80c) hcd64338023 die hd64338023d hd64338023( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338023e hd64338023( *** )f 80-pin qfp (fp-80b) hd64338023wi hd64338023( *** )w 80-pin tqfp (tfp-80c)
rev. 4.00, 05/03, page 550 of 562 product type product code mark code package (package code) h8/38022 hd64338022h hd64338022( *** )h 80-pin qfp (fp-80a) h8/38024 group mask rom versions regular specifications hd64338022f hd64338022( *** )f 80-pin qfp (fp-80b) hd64338022w hd64338022( *** )w 80-pin tqfp (tfp-80c) hcd64338022 die hd64338022d hd64338022( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338022e hd64338022( *** )f 80-pin qfp (fp-80b) hd64338022wi hd64338022( *** )w 80-pin tqfp (tfp-80c) h8/38021 hd64338021h hd64338021( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338021f hd64338021( *** )f 80-pin qfp (fp-80b) hd64338021w hd64338021( *** )w 80-pin tqfp (tfp-80c) hcd64338021 die hd64338021d hd64338021( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338021e hd64338021( *** )f 80-pin qfp (fp-80b) hd64338021wi hd64338021( *** )w 80-pin tqfp (tfp-80c) h8/38020 hd64338020h hd64338020( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338020f hd64338020( *** )f 80-pin qfp (fp-80b) hd64338020w hd64338020( *** )w 80-pin tqfp (tfp-80c) hcd64338020 die hd64338020d hd64338020( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338020e hd64338020( *** )f 80-pin qfp (fp-80b) hd64338020wi hd64338020( *** )w 80-pin tqfp (tfp-80c) h8/38024s hd64338024sh hd64338024( *** )h 80-pin qfp (fp-80a) h8/38024s group mask rom versions regular specifications hd64338024sw hd64338024( *** )w 80-pin tqfp (tfp-80c) hd64338024slpv 338024s( *** )lpv 85-pin tflga (tlp-85v) hcd64338024s die hd64338024sd hd64338024( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338024swi hd64338024( *** )w 80-pin tqfp (tfp-80c) hd64338024slpiv 338024s( *** )lpiv 85-pin tflga (tlp-85v) h8/38023s hd64338023sh hd64338023( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338023sw hd64338023( *** )w 80-pin tqfp (tfp-80c) hd64338023slpv 338023s( *** )lpv 85-pin tflga (tlp-85v) hcd64338023s die hd64338023sd hd64338023( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338023swi hd64338023( *** )w 80-pin tqfp (tfp-80c) hd64338023slpiv 338023s( *** )lpiv 85-pin tflga (tlp-85v) h8/38022s hd64338022sh hd64338022( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338022sw hd64338022( *** )w 80-pin tqfp (tfp-80c) hd64338022slpv 338022s( *** )lpv 85-pin tflga (tlp-85v) hcd64338022s die hd64338022sd hd64338022( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338022swi hd64338022( *** )w 80-pin tqfp (tfp-80c) hd64338022slpiv 338022s( *** )lpiv 85-pin tflga (tlp-85v)
rev. 4.00, 05/03, page 551 of 562 product type product code mark code package (package code) h8/38021s hd64338021sh hd64338021( *** )h 80-pin qfp (fp-80a) h8/38024s group mask rom versions regular specifications hd64338021sw hd64338021( *** )w 80-pin tqfp (tfp-80c) hd64338021slpv 338021s( *** )lpv 85-pin tflga (tlp-85v) hcd64338021s die hd64338021sd hd64338021( *** )h 80-pin qfp (fp-80a) wide-range specifications hd64338021swi hd64338021( *** )w 80-pin tqfp (tfp-80c) hd64338021slpiv 338021s( *** )lpiv 85-pin tflga (tlp-85v) h8/38020s hd64338020sh hd64338020( *** )h 80-pin qfp (fp-80a) mask rom versions regular specifications hd64338020sw hd64338020( *** )w 80-pin tqfp (tfp-80c) hd64338020slpv 338020s( *** )lpv 85-pin tflga (tlp-85v) hcd64338020s die hd64338020sd hd64338020( *** )h 80-pin qfp (fp-80a) hd64338020swi hd64338020( *** )w 80-pin tqfp (tfp-80c) wide-range specifications hd64338020slpiv 338020s( *** )lpiv 85-pin tflga (tlp-85v) note: ( *** ) is the rom code. an 85-pin version of the tflga (tlp-85v) is under development.
rev. 4.00, 05/03, page 552 of 562 appendix f package dimensions dimensional drawings of the h8/38024 group and h8/38024s group packages fp-80a, fp-80b, and tfp-80c are shown in figures f.1, f.2, and f.3 below. package code jedec jeita mass (reference value) fp-80a conforms 1.2 g * dimension including the plating thickness base material dimension 60 0 8 0.10 0.12 m 17.2 0.3 41 61 80 1 20 40 21 17.2 0.3 * 0.32 0.08 0.65 3.05 max 1.6 0.8 0.3 14 2.70 * 0.17 0.05 0.10 0.15 0.10 0.83 0.30 0.06 0.15 0.04 unit: mm figure f.1 fp-80a package dimensions
rev. 4.00, 05/03, page 553 of 562 package code jedec jeita mass (reference value) fp-80b 1.7 g * dimension including the plating thickness base material dimension 0.15 m 0 10 * 0.37 0.08 * 0.17 0.05 3.10 max 1.2 0.2 24.8 0.4 20 64 41 40 25 24 1 80 65 18.8 0.4 14 0.15 0.8 2.70 2.4 0.20 0.10 0.20 0.8 1.0 0.35 0.06 0.15 0.04 unit: mm figure f.2 fp-80b package dimensions
rev. 4.00, 05/03, page 554 of 562 package code jedec jeita mass (reference value) tfp-80c conforms 0.4 g * dimension including the plating thickness base material dimension 0.10 m 0.10 0.5 0.1 0 8 1.20 max 14.0 0.2 0.5 12 14.0 0.2 60 41 120 80 61 21 40 * 0.17 0.05 1.0 * 0.22 0.05 0.10 0.10 1.00 1.25 0.20 0.04 0.15 0.04 unit: mm figure f.3 tfp-80c package dimensions
rev. 4.00, 05/03, page 555 of 562 7.0 7.0 0.15 4 0.20 ca 0.20 c b a b 0.575 0.575 1.20 max 0.2 c 0.10 c c 0.08 c m a b 85 0.35 0.05 1 3 75 92 64 8 10 a c e g j b d f h 0.65 0.65 k (flatness of land portion) unit: mm figure f.4 tlp-85v package dimensions (under development)
rev. 4.00, 05/03, page 556 of 562 appendix g specifications of chip form the specifications of the chip form of the hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020 are shown in figure g.1. the specifications of the chip form of the hcd64f38024 and hcd64f38024r are shown in figure g.2. the specifications of the chip form of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s are shown in figure g.3. x-direction: 3.99 0.05 y-direction: 3.99 0.05 maximum plain x-direction: 3.99 0.25 y-direction: 3.99 0.25 0.28 0.02 max 0.03 unit: mm figure g.1 chip sectional figure of the hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020 x-direction: 3.84 0.05 y-direction: 4.24 0.05 maximum plain x-direction: 3.84 0.25 y-direction: 4.24 0.25 0.28 0.02 max 0.03 unit: mm figure g.2 chip sectional figure of the hcd64f38024 and hcd64f38024r
rev. 4.00, 05/03, page 557 of 562 x-direction: 2.91 0.05 y-direction: 2.91 0.05 maximum plain x-direction: 2.91 0.25 y-direction: 2.91 0.25 0.28 0.02 max 0.03 unit: mm figure g.3 chip sectional figure of the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s
rev. 4.00, 05/03, page 558 of 562 appendix h form of bonding pads the form of the bonding pads for the hcd64338024, hcd64338023, hcd64338022, hcd64338021, hcd64338020, hcd64f38024, hcd64f38024r, hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s is shown in figure h.1. bonding area metal layer 5 mm 72 mm 5 mm 72 mm figure h.1 bonding pad form
rev. 4.00, 05/03, page 559 of 562 appendix i specifications of chip tray the specifications of the chip tray for the hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020 are shown in figure i.1. the specifications of the chip tray for the hcd64f38024 and hcd64f38024r are shown in figure i.2. the specifications of the chip tray for the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s are shown in figure i.3. chip direction chip type name chip tray name dainippon-ink-&-chemicals-inc. type: ct015 carved code: tct45-060p x-x cross section unit: mm 0.6 0.1 6.2 0.1 6.9 0.15 4.0 0.1 6.2 0.1 6.9 0.1 xx 3.99 3.99 51 51 4.5 0.05 4.5 0.05 1.8 0.1 figure i.1 specifications of chip tray for the hcd64338024, hcd64338023, hcd64338022, hcd64338021, and hcd64338020
rev. 4.00, 05/03, page 560 of 562 chip direction chip type name chip tray name dainippon-ink-&-chemicals-inc. type: ct015 carved code: tct45-060p x-x cross section unit: mm 0.6 0.1 6.2 0.1 6.9 0.1 4.0 0.1 6.2 0.1 6.9 0.1 xx 4.24 3.84 51 51 4.5 0.05 1.8 0.1 4.5 0.05 figure i.2 specifications of chip tray for the hcd64f38024 and hcd64f38024r
rev. 4.00, 05/03, page 561 of 562 chip direction chip type name chip tray name dainippon-ink-&-chemicals-inc. type: ct022 carved code: tct036036-060 x-x cross section unit: mm 0.6 0.1 4.48 0.1 5.34 0.1 4.0 0.1 4.48 0.1 5.34 0.1 xx 2.91 2.91 51 51 3.6 0.05 3.6 0.05 1.8 0.1 figure i.3 specifications of chip tray for the hcd64338024s, hcd64338023s, hcd64338022s, hcd64338021s, and hcd64338020s
rev. 4.00, 05/03, page 562 of 562
h8/38024, h8/38024s, h8/38024f-ztat ? ? ? ? group hardware manual publication date: 1st edition, november 2000 rev.4.00, may 26, 2003 published by: sales strategic planning div. renesas technology corp. edited by: technical documentation & information department renesas kodaira semiconductor co., ltd. ?2000, 2003 renesas technology corp. all rights reserved. printed in japan.
colophon 0.0 http://www.renesas.com sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan
h8/38024, h8/38024s, h8/38024f-ztat group hardware manual rej09b0042-0400o

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